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Searched refs:MCOperand (Results 1 – 25 of 122) sorted by relevance

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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp539 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
545 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
623 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDaddiGroupBranch()
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
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/external/llvm/include/llvm/MC/
DMCInst.h33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand createReg(unsigned Reg) { in createReg()
112 MCOperand Op; in createReg()
117 static MCOperand createImm(int64_t Val) { in createImm()
118 MCOperand Op; in createImm()
123 static MCOperand createFPImm(double Val) { in createFPImm()
124 MCOperand Op; in createFPImm()
129 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
130 MCOperand Op; in createExpr()
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DMCInstBuilder.h33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand()
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp79 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
84 return MCOperand::createExpr(expr); in createSparcMCOperand()
87 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
92 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
107 return MCOperand::createExpr(expr); in createPCXRelExprOp()
111 MCOperand &Callee, in EmitCall()
121 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
144 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
150 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
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DSparcMCInstLower.cpp31 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
66 return MCOperand::createExpr(expr); in LowerSymbolOperand()
69 static MCOperand LowerOperand(const MachineInstr *MI, in LowerOperand()
77 return MCOperand::createReg(MO.getReg()); in LowerOperand()
80 return MCOperand::createImm(MO.getImm()); in LowerOperand()
92 return MCOperand(); in LowerOperand()
104 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerSparcMachineInstrToMCInst()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp195 const MCOperand &Imm, int AlignSize) { in smallData()
271 const MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction()
278 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction()
281 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
292 MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction()
297 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction()
300 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
310 MCOperand &Ps = Inst.getOperand(1); in HexagonProcessInstruction()
320 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction()
331 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction()
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DHexagonMCInstLower.cpp34 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, in GetSymbolRef()
69 return MCOperand::createExpr(ME); in GetSymbolRef()
91 MCOperand MCO; in HexagonLowerToMC()
102 MCO = MCOperand::createReg(MO.getReg()); in HexagonLowerToMC()
108 MCO = MCOperand::createExpr( in HexagonLowerToMC()
114 MCO = MCOperand::createExpr( in HexagonLowerToMC()
118 MCO = MCOperand::createExpr in HexagonLowerToMC()
145 MCB.addOperand(MCOperand::createInst(MCI)); in HexagonLowerToMC()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
277 const MCOperand &MO = MI.getOperand(Op); in getSOImmOpValue()
310 const MCOperand &MO = MI.getOperand(Op); in getModImmOpValue()
529 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
561 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
591 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
628 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
641 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
653 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBRTargetOpValue()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp115 const MCOperand &Dst = MI->getOperand(0); in printInst()
116 const MCOperand &MO1 = MI->getOperand(1); in printInst()
117 const MCOperand &MO2 = MI->getOperand(2); in printInst()
118 const MCOperand &MO3 = MI->getOperand(3); in printInst()
138 const MCOperand &Dst = MI->getOperand(0); in printInst()
139 const MCOperand &MO1 = MI->getOperand(1); in printInst()
140 const MCOperand &MO2 = MI->getOperand(2); in printInst()
282 MCOperand NewReg; in printInst()
287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( in printInst()
321 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
204 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
218 const MCOperand &MO = MI.getOperand(OpIdx); in getLdStUImm12OpValue()
239 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrLabelOpValue()
266 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
267 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue()
292 const MCOperand &MO = MI.getOperand(OpIdx); in getCondBranchTargetOpValue()
314 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLiteralOpValue()
343 const MCOperand &MO = MI.getOperand(OpIdx); in getMoveWideImmOpValue()
362 const MCOperand &MO = MI.getOperand(OpIdx); in getTestBranchTargetOpValue()
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/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp354 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
359 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
367 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
372 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
377 Inst.addOperand(MCOperand::createImm(Extended)); in addSignedImmOperands()
557 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds4_6ImmOperands()
563 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds3_6ImmOperands()
759 for (MCOperand &I : MCI) in canonicalizeImmediates()
768 NewInst.addOperand(MCOperand::createExpr( in canonicalizeImmediates()
844 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyMCInstLower.cpp40 MCOperand WebAssemblyMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
53 return MCOperand::createExpr(Expr); in LowerSymbolOperand()
63 MCOperand MCOp; in Lower()
75 MCOp = MCOperand::createReg(WAReg); in Lower()
79 MCOp = MCOperand::createImm(MO.getImm()); in Lower()
86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat()); in Lower()
88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble()); in Lower()
94 MCOp = MCOperand::createExpr( in Lower()
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp184 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
252 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
255 MCOperand segmentReg; in translateSrcIndex()
256 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
277 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
543 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
546 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
549 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
552 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); in translateImmediate()
580 mcInst.addOperand(MCOperand::createImm(immediate)); in translateImmediate()
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/external/llvm/lib/Target/XCore/
DXCoreMCInstLower.cpp35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
71 return MCOperand::createExpr(MCSym); in LowerSymbolOperand()
78 return MCOperand::createExpr(Add); in LowerSymbolOperand()
81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
90 return MCOperand::createReg(MO.getReg()); in LowerOperand()
92 return MCOperand::createImm(MO.getImm() + offset); in LowerOperand()
104 return MCOperand(); in LowerOperand()
112 MCOperand MCOp = LowerOperand(MO); in Lower()
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp55 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
129 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) * 2 + Address)); in decodePCDBLOperand()
232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
233 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
243 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
254 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
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/external/llvm/lib/Target/BPF/
DBPFMCInstLower.cpp33 MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
41 return MCOperand::createExpr(Expr); in LowerSymbolOperand()
50 MCOperand MCOp; in Lower()
59 MCOp = MCOperand::createReg(MO.getReg()); in Lower()
62 MCOp = MCOperand::createImm(MO.getImm()); in Lower()
65 MCOp = MCOperand::createExpr( in Lower()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
578 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
583 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
588 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
593 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
598 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
603 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp762 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
765 TmpInst.addOperand(MCOperand::createExpr(HiSym)); in emitDirectiveCpLoad()
771 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
772 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
775 TmpInst.addOperand(MCOperand::createExpr(LoSym)); in emitDirectiveCpLoad()
781 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
782 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
783 TmpInst.addOperand(MCOperand::createReg(RegNo)); in emitDirectiveCpLoad()
822 Inst.addOperand(MCOperand::createReg(RegOrOffset)); in emitDirectiveCpsetup()
823 Inst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpsetup()
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/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp39 NopInst.addOperand(MCOperand::createImm(0)); in getNoopForMachoTarget()
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DARMMCInstLower.cpp27 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, in GetSymbolRef()
64 return MCOperand::createExpr(Expr); in GetSymbolRef()
69 MCOperand &MCOp) { in lowerOperand()
77 MCOp = MCOperand::createReg(MO.getReg()); in lowerOperand()
80 MCOp = MCOperand::createImm(MO.getImm()); in lowerOperand()
83 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( in lowerOperand()
108 MCOp = MCOperand::createFPImm(Val.convertToDouble()); in lowerOperand()
153 MCOperand MCOp; in LowerARMMachineInstrToMCInst()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp171 MI.addOperand(MCOperand::createInst(Inst)); in getInstruction()
308 MCOperand OPLow = MCOperand::createInst(MILow); in getSingleInstruction()
309 MCOperand OPHigh = MCOperand::createInst(MIHigh); in getSingleInstruction()
347 MCOperand &MCO = MI.getOperand(OpIndex); in getSingleInstruction()
476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass()
578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass()
602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass()
620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass()
878 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial()
903 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial()
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/external/llvm/lib/Target/AArch64/
DAArch64MCInstLower.h21 class MCOperand; variable
38 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
41 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
43 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
45 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
DAArch64MCInstLower.cpp44 MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO, in lowerSymbolOperandDarwin()
76 return MCOperand::createExpr(Expr); in lowerSymbolOperandDarwin()
79 MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO, in lowerSymbolOperandELF()
151 return MCOperand::createExpr(Expr); in lowerSymbolOperandELF()
154 MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
164 MCOperand &MCOp) const { in lowerOperand()
172 MCOp = MCOperand::createReg(MO.getReg()); in lowerOperand()
178 MCOp = MCOperand::createImm(MO.getImm()); in lowerOperand()
181 MCOp = MCOperand::createExpr( in lowerOperand()
211 MCOperand MCOp; in Lower()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1676 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1678 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1680 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1687 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1692 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
1697 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
1702 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
1707 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands()
1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp93 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
156 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
168 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
181 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
194 const MCOperand &MO = MI.getOperand(OpNo); in getAbsCondBrEncoding()
206 const MCOperand &MO = MI.getOperand(OpNo); in getImm16Encoding()
223 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIEncoding()
242 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIXEncoding()
262 const MCOperand &MO = MI.getOperand(OpNo); in getSPE8DisEncoding()
278 const MCOperand &MO = MI.getOperand(OpNo); in getSPE4DisEncoding()
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