| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 345 bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
347 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
351 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| D | HexagonMCDuplexInfo.cpp | 575 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
587 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
593 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
615 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
645 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
646 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
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| D | HexagonMCInstrInfo.h | 198 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
234 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1180 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa, in checkInstOffsetsDoNotOverlap() argument
1185 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
1187 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() && in checkInstOffsetsDoNotOverlap()
1189 unsigned Width0 = (*MIa->memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1200 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() argument
1203 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) && in areMemAccessesTriviallyDisjoint()
1208 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1212 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1220 if (isDS(*MIa)) { in areMemAccessesTriviallyDisjoint()
1222 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
[all …]
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| D | SIInstrInfo.h | 65 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
137 MachineInstr *MIa, MachineInstr *MIb,
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1352 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1354 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 568 const DataLayout &DL, MachineInstr *MIa, in MIsNeedChainEdge() argument
570 const MachineFunction *MF = MIa->getParent()->getParent(); in MIsNeedChainEdge()
574 if (MIa == MIb) in MIsNeedChainEdge()
578 if ((MIa->mayLoad() || MIa->mayStore()) && in MIsNeedChainEdge()
580 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA)) in MIsNeedChainEdge()
584 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
587 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL)) in MIsNeedChainEdge()
592 if (!MIa->mayStore() && !MIb->mayStore()) in MIsNeedChainEdge()
599 MachineMemOperand *MMOa = *MIa->memoperands_begin(); in MIsNeedChainEdge()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
276 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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| D | HexagonInstrInfo.cpp | 1391 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() argument
1396 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1397 MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1402 if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1406 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA); in areMemAccessesTriviallyDisjoint()
1775 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa, in isDuplexPair() argument
1777 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa); in isDuplexPair()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 843 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb, in mayAlias() argument
846 if (!MIa->mayStore() && !MIb->mayStore()) in mayAlias()
850 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore()) in mayAlias()
853 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
856 static bool mayAlias(MachineInstr *MIa, in mayAlias() argument
860 if (mayAlias(MIa, MIb, TII)) in mayAlias()
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| D | AArch64InstrInfo.h | 56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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| D | AArch64InstrInfo.cpp | 615 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, in areMemAccessesTriviallyDisjoint() argument
623 assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
626 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
627 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
635 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-GB/ |
| D | en-GB_kh0_kpdf_mgc.pkb | 2821 F�b���������� ����!�.DH=.C0H%1PY^Ec<12*.,'.,MIa�<-HGI@ETKMTRckmayt�NS9�l�SJS`[gcG\VQkrqcce…
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