| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 58 MachineRegisterInfo &MRI) { in IsRegInClass()
60 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
68 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
72 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
76 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
77 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
80 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
81 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 72 MachineRegisterInfo *MRI; member in __anond1040a7e0111::AArch64AdvSIMDScalar
113 const MachineRegisterInfo *MRI) { in isGPR64() argument
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
122 const MachineRegisterInfo *MRI) { in isFPR64() argument
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
136 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
153 MRI) && in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
157 MRI) && in getSrcFromCopy()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 116 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVGPROperands() local
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
131 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
137 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
145 MRI.getRegClass(DstReg) : in getCopyRegClasses()
179 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
186 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence()
189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg); in foldVGPRCopyIntoRegSequence()
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
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| D | SIShrinkInstructions.cpp | 76 const MachineRegisterInfo &MRI) { in isVGPR() argument
81 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
88 const MachineRegisterInfo &MRI) { in canShrink() argument
102 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
139 MachineRegisterInfo &MRI, bool TryToCommute = true) { in foldImmediates() argument
141 if (!MRI.isSSA()) in foldImmediates()
159 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
163 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { in foldImmediates()
165 MachineInstr *Def = MRI.getUniqueVRegDef(Reg); in foldImmediates()
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| D | SIInstrInfo.cpp | 922 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); in commuteInstructionImpl() local
923 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) in commuteInstructionImpl()
1048 unsigned Reg, MachineRegisterInfo *MRI) const { in FoldImmediate()
1049 if (!MRI->hasOneNonDBGUse(Reg)) in FoldImmediate()
1070 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
1074 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
1119 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
1131 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
1135 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
1161 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); in FoldImmediate()
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| D | SIFrameLowering.cpp | 99 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue() local
100 MRI.addLiveIn(PreloadedScratchWaveOffsetReg); in emitPrologue()
104 MRI.addLiveIn(PreloadedPrivateBufferReg); in emitPrologue()
119 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue() local
127 if (!MRI.isPhysRegUsed(Reg)) { in emitPrologue()
128 assert(MRI.isAllocatable(Reg)); in emitPrologue()
129 MRI.replaceRegWith(ScratchRsrcReg, Reg); in emitPrologue()
138 MachineRegisterInfo &MRI = MF.getRegInfo(); in emitPrologue() local
145 if (!MRI.isPhysRegUsed(Reg)) { in emitPrologue()
146 assert(MRI.isAllocatable(Reg) && in emitPrologue()
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| D | R600OptimizeVectorRegisters.cpp | 50 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { in isImplicitlyDef() argument
51 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
52 E = MRI.def_instr_end(); It != E; ++It) { in isImplicitlyDef()
55 if (MRI.isReserved(Reg)) { in isImplicitlyDef()
67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() argument
72 if (isImplicitlyDef(MRI, MO.getReg())) in RegSeqInfo()
87 MachineRegisterInfo *MRI; member in __anond2fd63d90111::R600VectorRegMerger
191 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); in RebuildVector()
218 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), in RebuildVector()
219 E = MRI->use_instr_end(); It != E; ++It) { in RebuildVector()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegColoring.cpp | 63 static float computeWeight(const MachineRegisterInfo *MRI, in computeWeight() argument
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
86 MachineRegisterInfo *MRI = &MF.getRegInfo(); in runOnMachineFunction() local
93 unsigned NumVRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
103 if (MRI->use_empty(VReg)) in runOnMachineFunction()
108 LI->weight = computeWeight(MRI, MBFI, VReg); in runOnMachineFunction()
119 [MRI](LiveInterval *LHS, LiveInterval *RHS) { in runOnMachineFunction()
120 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) in runOnMachineFunction()
121 return MRI->isLiveIn(LHS->reg); in runOnMachineFunction()
139 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); in runOnMachineFunction()
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); in runOnMachineFunction()
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); in runOnMachineFunction()
115 AddLiveIn(&MF, MRI, new_reg, virt_reg); in runOnMachineFunction()
123 MachineRegisterInfo & MRI, in AddLiveIn() argument
127 if (!MRI.isLiveIn(physReg)) { in AddLiveIn()
128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg)); in AddLiveIn()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 126 MachineRegisterInfo *MRI; member in __anon2734e12b0111::PeepholeOptimizer
310 const MachineRegisterInfo &MRI; member in __anon2734e12b0111::ValueTracker
351 const MachineRegisterInfo &MRI, in ValueTracker() argument
355 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
357 Def = MRI.getVRegDef(Reg); in ValueTracker()
358 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
370 const MachineRegisterInfo &MRI, in ValueTracker() argument
374 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
423 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
429 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
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| D | RegAllocBase.cpp | 61 MRI = &vrm.getRegInfo(); in init()
65 MRI->freezeReservedRegs(vrm.getMachineFunction()); in init()
74 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in seedLiveRegs()
76 if (MRI->reg_nodbg_empty(Reg)) in seedLiveRegs()
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
131 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
142 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { in allocatePhysRegs()
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| D | LLVMTargetMachine.cpp | 46 MRI = TheTarget.createMCRegInfo(getTargetTriple().str()); in initAsmInfo()
56 TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str()); in initAsmInfo()
170 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitFile() local
178 getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); in addPassesToEmitFile()
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
186 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); in addPassesToEmitFile()
198 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); in addPassesToEmitFile()
200 getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); in addPassesToEmitFile()
251 const MCRegisterInfo &MRI = *getMCRegisterInfo(); in addPassesToEmitMC() local
253 getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); in addPassesToEmitMC()
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| D | RegisterPressure.cpp | 96 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
110 decreaseSetPressure(CurrSetPressure, MRI->getPressureSets(RegUnit)); in decreaseRegPressure()
162 void LiveRegSet::init(const MachineRegisterInfo &MRI) { in init() argument
163 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in init()
165 unsigned NumVirtRegs = MRI.getNumVirtRegs(); in init()
212 MRI = &MF->getRegInfo(); in init()
226 LiveRegs.init(*MRI); in init()
228 UntiedDefs.setUniverse(MRI->getNumVirtRegs()); in init()
304 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg)); in initLiveThru()
325 const MachineRegisterInfo &MRI, bool IgnoreDead = false);
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| D | OptimizePHIs.cpp | 33 MachineRegisterInfo *MRI; member in __anon093d81db0111::OptimizePHIs
69 MRI = &Fn.getRegInfo(); in runOnMachineFunction()
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); in IsSingleValuePHICycle()
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { in IsDeadPHICycle()
171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
174 MRI->replaceRegWith(OldReg, SingleValReg); in OptimizeBB()
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| D | MachineCSE.cpp | 48 MachineRegisterInfo *MRI; member in __anondf821cc60111::MachineCSE
132 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg); in INITIALIZE_PASS_DEPENDENCY()
133 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY()
155 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY()
156 if (!MRI->constrainRegClass(SrcReg, RC)) in INITIALIZE_PASS_DEPENDENCY()
162 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
233 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent())) in hasLivePhysRegDefUses()
285 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
376 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) { in isProfitableToCSE()
379 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { in isProfitableToCSE()
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| D | MachineSink.cpp | 59 MachineRegisterInfo *MRI; // Machine register information member in __anon953a4dc00111::MachineSinking
166 !MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
169 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
170 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
179 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
184 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
204 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
223 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
236 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in AllUsesDominatedByBlock()
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| D | VirtRegMap.cpp | 57 MRI = &mf.getRegInfo(); in runOnMachineFunction()
85 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
122 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
162 MachineRegisterInfo *MRI; member in __anon1700c3f70111::VirtRegRewriter
213 MRI = &MF->getRegInfo(); in runOnMachineFunction()
237 MRI->clearVirtRegs(); in runOnMachineFunction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 169 MachineRegisterInfo &MRI);
171 unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI);
173 unsigned NewSR, MachineRegisterInfo &MRI);
175 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
185 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
187 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
326 MachineRegisterInfo &MRI) { in replaceReg() argument
330 auto Begin = MRI.use_begin(OldR), End = MRI.use_end(); in replaceReg()
341 unsigned NewSR, MachineRegisterInfo &MRI) { in replaceRegWithSub() argument
345 auto Begin = MRI.use_begin(OldR), End = MRI.use_end(); in replaceRegWithSub()
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| D | HexagonGenPredicate.cpp | 66 HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) { in HexagonGenPredicate()
86 MachineRegisterInfo *MRI; member in __anon7eb497360111::HexagonGenPredicate
115 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
210 use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); in processPredicateGPR()
213 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in processPredicateGPR()
236 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in getPredRegFor()
250 unsigned NewPR = MRI->createVirtualRegister(PredRC); in getPredRegFor()
311 const MachineInstr *DefI = MRI->getVRegDef(PR.R); in isScalarPred()
318 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
404 Register NewPR = MRI->createVirtualRegister(PredRC); in convertToPredForm()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 62 MachineRegisterInfo *MRI; member
145 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
163 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
230 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end(); in eraseInstrWithNoUses()
262 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
263 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
282 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
283 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
314 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
357 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies()
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| D | MLxExpansionPass.cpp | 53 MachineRegisterInfo *MRI; member
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
120 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
160 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXPeephole.cpp | 83 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate() local
86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg()); in isCVTAToLocalCombinationCandidate()
108 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal() local
110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); in CombineCVTAToLocal()
121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) { in CombineCVTAToLocal()
144 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction() local
145 if (MRI.use_empty(NVPTX::VRFrame)) { in runOnMachineFunction()
146 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) { in runOnMachineFunction()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCTargetDesc.h | 39 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
46 const MCRegisterInfo &MRI,
49 const MCRegisterInfo &MRI,
52 const MCRegisterInfo &MRI,
55 const MCRegisterInfo &MRI,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.h | 60 const MCRegisterInfo &MRI,
64 const MCRegisterInfo &MRI,
67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
78 const MCRegisterInfo &MRI,
82 const MCRegisterInfo &MRI,
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| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| D | BPFMCCodeEmitter.cpp | 32 const MCRegisterInfo &MRI; member in __anonffff22b10111::BPFMCCodeEmitter
37 : MRI(mri), IsLittleEndian(IsLittleEndian) {} in BPFMCCodeEmitter()
64 const MCRegisterInfo &MRI, in createBPFMCCodeEmitter() argument
66 return new BPFMCCodeEmitter(MRI, true); in createBPFMCCodeEmitter()
70 const MCRegisterInfo &MRI, in createBPFbeMCCodeEmitter() argument
72 return new BPFMCCodeEmitter(MRI, false); in createBPFbeMCCodeEmitter()
80 return MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
159 Encoding = MRI.getEncodingValue(Op1.getReg()); in getMemoryOpValue()
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