Searched refs:Masked (Results 1 – 16 of 16) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | CaymanInstructions.td | 114 let DST_SEL_Y = 7; // Masked
115 let DST_SEL_Z = 7; // Masked
116 let DST_SEL_W = 7; // Masked
124 let DST_SEL_Y = 7; // Masked
125 let DST_SEL_Z = 7; // Masked
126 let DST_SEL_W = 7; // Masked
136 let DST_SEL_Y = 7; // Masked
137 let DST_SEL_Z = 7; // Masked
138 let DST_SEL_W = 7; // Masked
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| D | EvergreenInstructions.td | 143 let DST_SEL_Y = 7; // Masked
144 let DST_SEL_Z = 7; // Masked
145 let DST_SEL_W = 7; // Masked
154 let DST_SEL_Y = 7; // Masked
155 let DST_SEL_Z = 7; // Masked
156 let DST_SEL_W = 7; // Masked
167 let DST_SEL_Y = 7; // Masked
168 let DST_SEL_Z = 7; // Masked
169 let DST_SEL_W = 7; // Masked
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| /external/opencv3/modules/cudaarithm/test/ |
| D | test_gpumat.cpp | 133 CUDA_TEST_P(GpuMat_SetTo, Masked) in CUDA_TEST_P() argument
201 CUDA_TEST_P(GpuMat_CopyTo, Masked) in CUDA_TEST_P() argument
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| /external/deqp/doc/testspecs/GLES2/ |
| D | functional.stencil.txt | 29 + Masked stencil comparison
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| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_bit.txt | 78 # Masked parity
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| /external/opencv3/doc/py_tutorials/py_imgproc/py_histograms/py_histogram_equalization/ |
| D | py_histogram_equalization.markdown | 143 2. [Masked Arrays in Numpy](http://docs.scipy.org/doc/numpy/reference/maskedarray.html)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 1002 let DST_SEL_Y = 7; // Masked
1003 let DST_SEL_Z = 7; // Masked
1004 let DST_SEL_W = 7; // Masked
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 1799 Value *Masked = nullptr; in FoldOrOfICmps() local
1806 Masked = Builder->CreateAnd(LAnd->getOperand(0), Mask); in FoldOrOfICmps()
1813 Masked = Builder->CreateAnd(LAnd->getOperand(1), Mask); in FoldOrOfICmps()
1816 if (Masked) in FoldOrOfICmps()
1817 return Builder->CreateICmp(ICmpInst::ICMP_NE, Masked, Mask); in FoldOrOfICmps()
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| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_bit.ll | 217 ; Masked parity
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 634 //===-------------------------- Masked Intrinsics -------------------------===//
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 100 # Vector Move Immediate Masked
101 # Vector Move Inverted Immediate Masked
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| /external/llvm/test/CodeGen/X86/ |
| D | vector-rotate-256.ll | 884 ; Masked Uniform Constant Rotates
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| D | vector-rotate-128.ll | 1408 ; Masked Uniform Constant Rotates
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| D | masked_gather_scatter.ll | 388 ; Masked gather for agregate types
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 7156 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG)) in lowerVectorShuffleAsBlend() local
7157 return Masked; in lowerVectorShuffleAsBlend()
8842 if (SDValue Masked = in lowerV4I32VectorShuffle() local
8844 return Masked; in lowerV4I32VectorShuffle()
9474 if (SDValue Masked = in lowerV8I16VectorShuffle() local
9476 return Masked; in lowerV8I16VectorShuffle()
9717 if (SDValue Masked = in lowerV16I8VectorShuffle() local
9719 return Masked; in lowerV16I8VectorShuffle()
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| /external/llvm/docs/ |
| D | LangRef.rst | 11295 Masked Vector Load and Store Intrinsics
11390 Masked Vector Gather and Scatter Intrinsics
11393 LLVM provides intrinsics for vector gather and scatter operations. They are similar to :ref:`Masked…
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