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Searched refs:MidVT (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp4208 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt); in getPromotedVectorElementType() local
4209 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType()
4210 return MidVT; in getPromotedVectorElementType()
4474 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4479 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op)); in PromoteNode()
4507 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4508 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
4528 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps); in PromoteNode()
4554 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4555 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
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DLegalizeFloatTypes.cpp467 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local
469 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7917 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local
7918 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine()
7923 MidVT, dl, in performConcatVectorsCombine()
7924 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
7925 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()