Searched refs:N01 (Results 1 – 6 of 6) sorted by relevance
| /external/clang/test/Modules/Inputs/stress1/ |
| D | common.h | 8 namespace N01 { struct S00; }
44 namespace N01 {
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| /external/clang/test/Modules/ |
| D | stress1.cpp | 131 int f() { return N01::S00('a').method00('b') + (int)N00::S00(42) + function00(42) + g(); } in f()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1723 SDValue N01 = N0.getOperand(1); in visitADD() local
1730 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); in visitADD()
3519 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
3523 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { in MatchBSwapHWord()
3532 SDValue N010 = N01.getOperand(0); in MatchBSwapHWord()
3535 SDValue N011 = N01.getOperand(1); in MatchBSwapHWord()
3542 if (!isBSwapHWordElement(N01, Parts)) in MatchBSwapHWord()
4322 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
4324 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) { in distributeTruncateThroughAnd()
4372 SDValue N01 = N0->getOperand(1); in visitSHL() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6418 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
6424 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
8716 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
8719 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2201 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
2207 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 25032 SDValue N01 = N0.getOperand(1); in PerformSRACombine() local
25033 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue(); in PerformSRACombine()
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