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Searched refs:NewVT (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp167 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_BITCAST() local
169 NewVT, N->getOperand(0)); in ScalarizeVecRes_BITCAST()
183 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_CONVERT_RNDSAT() local
185 return DAG.getConvertRndSat(NewVT, SDLoc(N), in ScalarizeVecRes_CONVERT_RNDSAT()
186 Op0, DAG.getValueType(NewVT), in ScalarizeVecRes_CONVERT_RNDSAT()
200 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_FP_ROUND() local
203 NewVT, Op, N->getOperand(1)); in ScalarizeVecRes_FP_ROUND()
1270 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local
1271 unsigned NewElts = NewVT.getVectorNumElements(); in SplitVecRes_VECTOR_SHUFFLE()
1328 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
[all …]
DLegalizeTypesGeneric.cpp225 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
238 NewVT, 2*OldElts), in ExpandRes_EXTRACT_VECTOR_ELT()
245 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
249 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
385 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
407 NewVT, NewElts.size()), in ExpandOp_BUILD_VECTOR()
DLegalizeVectorOps.cpp473 EVT NewVT; in PromoteFP_TO_INT() local
476 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteFP_TO_INT()
477 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!"); in PromoteFP_TO_INT()
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { in PromoteFP_TO_INT()
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0)); in PromoteFP_TO_INT()
DDAGCombiner.cpp2500 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHS() local
2501 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2502 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2503 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2504 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
2505 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2536 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHU() local
2537 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2538 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2539 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
[all …]
DSelectionDAG.cpp4206 EVT NewVT = VT; in FindOptimalMemOpLowering() local
4211 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in FindOptimalMemOpLowering()
4212 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && in FindOptimalMemOpLowering()
4213 TLI.isSafeMemOpType(NewVT.getSimpleVT())) in FindOptimalMemOpLowering()
4215 else if (NewVT == MVT::i64 && in FindOptimalMemOpLowering()
4219 NewVT = MVT::f64; in FindOptimalMemOpLowering()
4226 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
4227 if (NewVT == MVT::i8) in FindOptimalMemOpLowering()
4229 } while (!TLI.isSafeMemOpType(NewVT.getSimpleVT())); in FindOptimalMemOpLowering()
4231 NewVTSize = NewVT.getSizeInBits() / 8; in FindOptimalMemOpLowering()
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DLegalizeDAG.cpp3234 EVT NewVT = in ExpandNode() local
3237 assert(NewVT.bitsEq(VT)); in ExpandNode()
3240 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3241 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3245 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3261 VT = NewVT; in ExpandNode()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1059 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); in getVectorTypeBreakdownMVT() local
1060 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1061 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1062 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1064 unsigned NewVTSize = NewVT.getSizeInBits(); in getVectorTypeBreakdownMVT()
1070 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1072 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1429 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); in getVectorTypeBreakdown() local
1430 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1431 NewVT = EltTy; in getVectorTypeBreakdown()
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/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp4168 EVT NewVT) const { in shouldReduceLoadWidth()
6005 EVT NewVT = V0_LO.getValueType(); in ExpandHorizontalBinOp() local
6007 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
6008 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
6013 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); in ExpandHorizontalBinOp()
6015 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); in ExpandHorizontalBinOp()
6020 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); in ExpandHorizontalBinOp()
6024 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); in ExpandHorizontalBinOp()
7916 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
7917 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
[all …]
DX86ISelLowering.h873 EVT NewVT) const override;
/external/llvm/lib/Transforms/InstCombine/
DInstCombineCalls.cpp1594 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
1597 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
1598 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1523 EVT NewVT = MVT::v4i32; in LowerLOAD() local
1526 NewVT = VT; in LowerLOAD()
1529 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, in LowerLOAD()
DAMDGPUISelLowering.cpp440 EVT NewVT) const { in shouldReduceLoadWidth()
442 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
/external/llvm/include/llvm/Target/
DTargetLowering.h820 EVT NewVT) const { in shouldReduceLoadWidth() argument
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1855 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
1859 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
2047 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
2049 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
8059 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); in tryExtendDUPToExtractHigh() local
8063 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()), in tryExtendDUPToExtractHigh()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp6256 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local
6258 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()