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Searched refs:OUT_BATCH_REGVAL (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_blit.c80 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0); in emit_vtx_state()
82 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); in emit_vtx_state()
84 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE | in emit_vtx_state()
86 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0); in emit_vtx_state()
87 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0); in emit_vtx_state()
88 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY); in emit_vtx_state()
89 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); in emit_vtx_state()
90 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | in emit_vtx_state()
169 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | in emit_tx_setup()
171 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | in emit_tx_setup()
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Dradeon_cmdbuf.h94 #define OUT_BATCH_REGVAL(reg, val) \ macro
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_blit.c77 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0); in emit_vtx_state()
79 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); in emit_vtx_state()
82 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | in emit_vtx_state()
84 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); in emit_vtx_state()
85 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | in emit_vtx_state()
149 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); in emit_tx_setup()
150 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | in emit_tx_setup()
155 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO | in emit_tx_setup()
160 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST | in emit_tx_setup()
164 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat); in emit_tx_setup()
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Dradeon_cmdbuf.h94 #define OUT_BATCH_REGVAL(reg, val) \ macro