Searched refs:OddReg (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 912 const unsigned OddReg = CSRegs[i]; in determineCalleeSaves() local
914 assert((AArch64::GPR64RegClass.contains(OddReg) && in determineCalleeSaves()
916 (AArch64::FPR64RegClass.contains(OddReg) && in determineCalleeSaves()
920 const bool OddRegUsed = SavedRegs.test(OddReg); in determineCalleeSaves()
926 if (AArch64::GPR64RegClass.contains(OddReg)) { in determineCalleeSaves()
927 UnspilledCSGPRs.push_back(OddReg); in determineCalleeSaves()
930 UnspilledCSFPRs.push_back(OddReg); in determineCalleeSaves()
941 Reg = OddRegUsed ? EvenReg : OddReg; in determineCalleeSaves()
945 DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo)); in determineCalleeSaves()
948 assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) || in determineCalleeSaves()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1523 unsigned OddReg = MI->getOperand(1).getReg(); in FixInvalidRegPairOp() local
1525 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); in FixInvalidRegPairOp()
1565 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
1573 .addReg(OddReg, in FixInvalidRegPairOp()
1593 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1595 OddReg, OddDeadKill, false, in FixInvalidRegPairOp()
1603 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1618 OddReg, OddDeadKill, OddUndef, in FixInvalidRegPairOp()
1912 unsigned &OddReg, unsigned &BaseReg,
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