| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
190 assert(Offset2 > Offset1 in shouldScheduleLoadsNear()
195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 110 int64_t Offset1, int64_t Offset2,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 225 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
226 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
227 Offset1 == Offset2) in ClusterNeighboringLoads()
233 O2SMap.insert(std::make_pair(Offset2, User)); in ClusterNeighboringLoads()
234 Offsets.push_back(Offset2); in ClusterNeighboringLoads()
235 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| D | DAGCombiner.cpp | 14485 int64_t Offset1, Offset2; in isAlias() local
14491 Base2, Offset2, GV2, CV2); in isAlias()
14495 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
14496 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
14505 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); in isAlias()
14506 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
14507 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
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| D | SelectionDAG.cpp | 7053 int64_t Offset2 = 0; in isConsecutiveLoad() local
7055 bool isGA2 = TLI->isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); in isConsecutiveLoad()
7057 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 409 int64_t &Offset2) const override;
420 int64_t Offset1, int64_t Offset2,
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| D | X86InstrInfo.cpp | 6411 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr()
6508 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); in areLoadsFromSameBasePtr()
6516 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
6518 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
6519 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 216 int64_t &Offset2) const override;
227 int64_t Offset1, int64_t Offset2,
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| D | ARMBaseInstrInfo.cpp | 1547 int64_t &Offset2) const { in areLoadsFromSameBasePtr()
1608 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1627 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1632 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
1634 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.h | 118 int64_t Offset1, int64_t Offset2,
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| D | SIInstrInfo.h | 88 int64_t &Offset2) const override;
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 957 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
970 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 1159 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); in getOpcodeForOffset() local
1160 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) { in getOpcodeForOffset()
1170 if (isInt<20>(Offset) && isInt<20>(Offset2)) { in getOpcodeForOffset()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | SeparateConstOffsetFromGEP.cpp | 1247 Value *Offset2 = Second->getOperand(1); in swapGEPOperand() local
1248 First->setOperand(1, Offset2); in swapGEPOperand()
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| D | MemCpyOptimizer.cpp | 121 int64_t Offset2 = GetOffsetFromIndex(GEP2, Idx, VariableIdxFound, DL); in IsPointerOffset() local
124 Offset = Offset2-Offset1; in IsPointerOffset()
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| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 1732 uint64_t Offset2 = Offset.getLimitedValue(); in optimizeCallInst() local
1733 if ((Offset2 & (PrefAlign-1)) != 0) in optimizeCallInst()
1737 DL->getTypeAllocSize(AI->getAllocatedType()) >= MinSize + Offset2) in optimizeCallInst()
1747 MinSize + Offset2) in optimizeCallInst()
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| /external/clang/tools/c-index-test/ |
| D | c-index-test.c | 1435 long long Offset2 = clang_Cursor_getOffsetOfField(cursor); in PrintTypeSize() local
1436 if (Offset == Offset2){ in PrintTypeSize()
1440 printf(" [offsetof=%lld/%lld]", Offset, Offset2); in PrintTypeSize()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9255 int64_t Offset1 = 0, Offset2 = 0; in isConsecutiveLSLoc() local
9257 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG); in isConsecutiveLSLoc()
9258 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes)) in isConsecutiveLSLoc()
9265 Offset2 = 0; in isConsecutiveLSLoc()
9267 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); in isConsecutiveLSLoc()
9269 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLSLoc()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 8626 int Offset1, int Offset2, int Offset4, int Offset8> {
8652 !cast<Operand>("GPR64pi" # Offset2)>;
8655 !cast<Operand>("GPR64pi" # Offset2)>;
8671 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8672 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
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