| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 89 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in adjustStackPointer() local
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
96 .addReg(OffsetReg); in adjustStackPointer()
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
104 .addReg(OffsetReg) in adjustStackPointer()
150 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in emitEpilogue() local
159 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
164 .addReg(OffsetReg); in emitEpilogue()
166 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
172 .addReg(OffsetReg) in emitEpilogue()
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| D | WebAssemblyRegisterInfo.cpp | 78 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in eliminateFrameIndex() local
79 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32), OffsetReg) in eliminateFrameIndex()
81 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32), OffsetReg) in eliminateFrameIndex()
83 .addReg(OffsetReg); in eliminateFrameIndex()
84 MI.getOperand(FIOperandNum).ChangeToRegister(OffsetReg, /*IsDef=*/false); in eliminateFrameIndex()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.cpp | 124 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
125 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
130 Address, OffsetReg); in expandPostRAPseudo()
138 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
139 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
145 OffsetReg); in expandPostRAPseudo()
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| D | R600InstrInfo.h | 43 unsigned OffsetReg,
49 unsigned OffsetReg,
225 unsigned OffsetReg) const override;
230 unsigned OffsetReg) const override;
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| D | AMDGPUInstrInfo.h | 177 unsigned OffsetReg) const = 0;
185 unsigned OffsetReg) const = 0;
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| D | R600InstrInfo.cpp | 1108 unsigned OffsetReg) const { in buildIndirectWrite()
1109 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1115 unsigned OffsetReg, in buildIndirectWrite() argument
1126 AMDGPU::AR_X, OffsetReg); in buildIndirectWrite()
1140 unsigned OffsetReg) const { in buildIndirectRead()
1141 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1147 unsigned OffsetReg, in buildIndirectRead() argument
1159 OffsetReg); in buildIndirectRead()
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| D | SIInstrInfo.h | 431 unsigned OffsetReg) const override;
437 unsigned OffsetReg) const override;
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| D | SIInstrInfo.cpp | 2984 unsigned Address, unsigned OffsetReg) const { in buildIndirectWrite()
2993 .addReg(OffsetReg) in buildIndirectWrite()
3002 unsigned Address, unsigned OffsetReg) const { in buildIndirectRead()
3011 .addReg(OffsetReg) in buildIndirectRead()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 194 unsigned OffsetReg; member
250 return Mem.OffsetReg; in getMemOffsetReg()
406 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
415 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
427 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 480 unsigned OffsetReg = 0; in ReduceLoadStore() local
484 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
519 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
522 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 533 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
534 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 693 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
707 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| D | MipsISelLowering.cpp | 2072 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2074 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2077 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 60 unsigned OffsetReg; member in __anoncec764240111::AArch64FastISel::Address
67 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; } in Address()
83 OffsetReg = Reg; in setOffsetReg()
86 return OffsetReg; in getOffsetReg()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2557 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
2564 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 21074 unsigned OffsetReg = 0; in EmitVAARG64WithCustomInserter() local
21129 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARG64WithCustomInserter()
21130 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARG64WithCustomInserter()
21140 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
21151 assert(OffsetReg != 0); in EmitVAARG64WithCustomInserter()
21167 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
21178 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
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