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Searched refs:Op0Reg (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp218 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
222 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
226 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
3473 unsigned Op0Reg = getRegForValue(II->getOperand(0)); in fastLowerIntrinsicCall() local
3474 if (!Op0Reg) in fastLowerIntrinsicCall()
3478 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall()
3875 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr() argument
[all …]
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1704 unsigned Op0Reg = getRegForValue(Op0); in selectShift() local
1705 if (!Op0Reg) in selectShift()
1716 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
1719 Op0Reg = TempReg; in selectShift()
1739 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
1762 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1207 unsigned Op0Reg = getRegForValue(Op0); in X86FastEmitCompare() local
1208 if (Op0Reg == 0) return false; in X86FastEmitCompare()
1220 .addReg(Op0Reg) in X86FastEmitCompare()
1232 .addReg(Op0Reg) in X86FastEmitCompare()
1575 unsigned Op0Reg = getRegForValue(I->getOperand(0)); in X86SelectShift() local
1576 if (Op0Reg == 0) return false; in X86SelectShift()
1592 .addReg(Op0Reg); in X86SelectShift()
1684 unsigned Op0Reg = getRegForValue(I->getOperand(0)); in X86SelectDivRem() local
1685 if (Op0Reg == 0) in X86SelectDivRem()
1693 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()