| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 260 unsigned &Op3) { in Decode3OpInstruction() argument
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
539 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
552 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
565 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAGInfo.h | 52 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy() argument
69 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
85 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemset() argument
98 SDValue Op3, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
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| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
| D | reduce.hpp | 157 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
162 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
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| /external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
| D | reduce.hpp | 71 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
75 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in blockReduce() argument
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in blockReduce()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandPredSpillCode.cpp | 104 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. in runOnMachineFunction() local
108 Hexagon::C6)->addOperand(Op3); in runOnMachineFunction()
226 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. in runOnMachineFunction() local
229 Hexagon::C6)->addOperand(Op3); in runOnMachineFunction()
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| D | HexagonSplitDouble.cpp | 880 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
881 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
882 int64_t Sh64 = Op3.getImm(); in splitAslOr()
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| D | HexagonInstrInfo.cpp | 959 const MachineOperand &Op3 = MI->getOperand(3); in expandPostRAPseudo() local
963 unsigned Rt = Op3.getReg(); in expandPostRAPseudo()
967 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
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| /external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
| D | reduce.hpp | 168 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
173 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
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| /external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
| D | reduce.hpp | 186 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
191 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
207 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
211 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 30 SDValue Op3, unsigned Align, bool isVolatile,
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 920 SDValue Op3);
922 SDValue Op3, SDValue Op4);
924 SDValue Op3, SDValue Op4, SDValue Op5);
936 SDValue Op1, SDValue Op2, SDValue Op3);
951 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
953 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
974 SDValue Op1, SDValue Op2, SDValue Op3);
983 SDValue Op1, SDValue Op2, SDValue Op3);
990 SDValue Op3);
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| D | SelectionDAGNodes.h | 844 const SDValue &Op2, const SDValue &Op3) {
852 Ops[3].setInitial(Op3);
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| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/ |
| D | reduce.hpp | 69 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
73 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in warpReduce() argument
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in warpReduce()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 69 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
76 switch (Op3.getImm()) { in printInst()
109 if (Op2.isImm() && Op3.isImm()) { in printInst()
113 int64_t imms = Op3.getImm(); in printInst()
143 if (Op2.getImm() > Op3.getImm()) { in printInst()
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 60 SDValue Op3, unsigned Align,
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/ |
| D | reduce.hpp | 66 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
70 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in reduce() argument
75 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in reduce()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3787 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3788 if (Op2.isReg() && Op3.isImm()) { in MatchAndEmitInstruction()
3789 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3809 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
3810 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
3811 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3873 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3876 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3877 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3892 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 20 bit Op3 = 0;
45 let TSFlags{5} = Op3;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5766 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
5767 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
5773 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
5774 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
5780 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5781 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
5852 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
5854 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
5909 SDValue Op3) { in SelectNodeTo() argument
5911 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
[all …]
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| D | SelectionDAGBuilder.cpp | 4382 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4388 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
4398 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4404 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
4412 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
4418 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, in visitIntrinsicCall()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 22 bit Op3 = 0;
35 let TSFlags{5} = Op3;
107 let Op3 = 1;
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 1769 if (const ConstantFP *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall() local
1776 Op3->getValueAPF(), in ConstantFoldScalarCall()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2988 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
3000 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
3008 OutOps.push_back(Op3); in SelectInlineAsmMemoryOperand()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5404 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm() local
5406 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
5409 auto Op3Reg = Op3.getReg(); in tryConvertingToTwoOperandForm()
5923 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction() local
5924 if (Op3.isMem()) { in ParseInstruction()
|