1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
3 
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 
22 using namespace llvm;
23 
24 namespace {
25 
26 class MipsFastISel final : public FastISel {
27 
28   // All possible address modes.
29   class Address {
30   public:
31     typedef enum { RegBase, FrameIndexBase } BaseKind;
32 
33   private:
34     BaseKind Kind;
35     union {
36       unsigned Reg;
37       int FI;
38     } Base;
39 
40     int64_t Offset;
41 
42     const GlobalValue *GV;
43 
44   public:
45     // Innocuous defaults for our address.
Address()46     Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
setKind(BaseKind K)47     void setKind(BaseKind K) { Kind = K; }
getKind() const48     BaseKind getKind() const { return Kind; }
isRegBase() const49     bool isRegBase() const { return Kind == RegBase; }
isFIBase() const50     bool isFIBase() const { return Kind == FrameIndexBase; }
setReg(unsigned Reg)51     void setReg(unsigned Reg) {
52       assert(isRegBase() && "Invalid base register access!");
53       Base.Reg = Reg;
54     }
getReg() const55     unsigned getReg() const {
56       assert(isRegBase() && "Invalid base register access!");
57       return Base.Reg;
58     }
setFI(unsigned FI)59     void setFI(unsigned FI) {
60       assert(isFIBase() && "Invalid base frame index access!");
61       Base.FI = FI;
62     }
getFI() const63     unsigned getFI() const {
64       assert(isFIBase() && "Invalid base frame index access!");
65       return Base.FI;
66     }
67 
setOffset(int64_t Offset_)68     void setOffset(int64_t Offset_) { Offset = Offset_; }
getOffset() const69     int64_t getOffset() const { return Offset; }
setGlobalValue(const GlobalValue * G)70     void setGlobalValue(const GlobalValue *G) { GV = G; }
getGlobalValue()71     const GlobalValue *getGlobalValue() { return GV; }
72   };
73 
74   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
75   /// make the right decision when generating code for different targets.
76   const TargetMachine &TM;
77   const MipsSubtarget *Subtarget;
78   const TargetInstrInfo &TII;
79   const TargetLowering &TLI;
80   MipsFunctionInfo *MFI;
81 
82   // Convenience variables to avoid some queries.
83   LLVMContext *Context;
84 
85   bool fastLowerCall(CallLoweringInfo &CLI) override;
86   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
87 
88   bool TargetSupported;
89   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
90   // floating point but not reject doing fast-isel in other
91   // situations
92 
93 private:
94   // Selection routines.
95   bool selectLogicalOp(const Instruction *I);
96   bool selectLoad(const Instruction *I);
97   bool selectStore(const Instruction *I);
98   bool selectBranch(const Instruction *I);
99   bool selectSelect(const Instruction *I);
100   bool selectCmp(const Instruction *I);
101   bool selectFPExt(const Instruction *I);
102   bool selectFPTrunc(const Instruction *I);
103   bool selectFPToInt(const Instruction *I, bool IsSigned);
104   bool selectRet(const Instruction *I);
105   bool selectTrunc(const Instruction *I);
106   bool selectIntExt(const Instruction *I);
107   bool selectShift(const Instruction *I);
108   bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
109 
110   // Utility helper routines.
111   bool isTypeLegal(Type *Ty, MVT &VT);
112   bool isTypeSupported(Type *Ty, MVT &VT);
113   bool isLoadTypeLegal(Type *Ty, MVT &VT);
114   bool computeAddress(const Value *Obj, Address &Addr);
115   bool computeCallAddress(const Value *V, Address &Addr);
116   void simplifyAddress(Address &Addr);
117 
118   // Emit helper routines.
119   bool emitCmp(unsigned DestReg, const CmpInst *CI);
120   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
121                 unsigned Alignment = 0);
122   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
123                  MachineMemOperand *MMO = nullptr);
124   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
125                  unsigned Alignment = 0);
126   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
128 
129                   bool IsZExt);
130   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
131 
132   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
134                        unsigned DestReg);
135   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
136                        unsigned DestReg);
137 
138   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
139 
140   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
141                          const Value *RHS);
142 
143   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
144   unsigned materializeGV(const GlobalValue *GV, MVT VT);
145   unsigned materializeInt(const Constant *C, MVT VT);
146   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
147   unsigned materializeExternalCallSym(MCSymbol *Syn);
148 
emitInst(unsigned Opc)149   MachineInstrBuilder emitInst(unsigned Opc) {
150     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
151   }
emitInst(unsigned Opc,unsigned DstReg)152   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
153     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
154                    DstReg);
155   }
emitInstStore(unsigned Opc,unsigned SrcReg,unsigned MemReg,int64_t MemOffset)156   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
157                                     unsigned MemReg, int64_t MemOffset) {
158     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
159   }
emitInstLoad(unsigned Opc,unsigned DstReg,unsigned MemReg,int64_t MemOffset)160   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
161                                    unsigned MemReg, int64_t MemOffset) {
162     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
163   }
164 
165   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
166                            const TargetRegisterClass *RC,
167                            unsigned Op0, bool Op0IsKill,
168                            unsigned Op1, bool Op1IsKill);
169 
170   // for some reason, this default is not generated by tablegen
171   // so we explicitly generate it here.
172   //
fastEmitInst_riir(uint64_t inst,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,uint64_t imm1,uint64_t imm2,unsigned Op3,bool Op3IsKill)173   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
174                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
175                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
176     return 0;
177   }
178 
179   // Call handling routines.
180 private:
181   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
182   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
183                        unsigned &NumBytes);
184   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
185 
186 public:
187   // Backend specific FastISel code.
MipsFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo)188   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
189                         const TargetLibraryInfo *libInfo)
190       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
191         Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
192         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
193     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
194     Context = &funcInfo.Fn->getContext();
195     bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
196     TargetSupported =
197         ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
198         (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
199     UnsupportedFPMode = Subtarget->isFP64bit();
200   }
201 
202   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
203   unsigned fastMaterializeConstant(const Constant *C) override;
204   bool fastSelectInstruction(const Instruction *I) override;
205 
206 #include "MipsGenFastISel.inc"
207 };
208 } // end anonymous namespace.
209 
210 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
211                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
212                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
213 
CC_MipsO32_FP32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)214 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
215                             CCValAssign::LocInfo LocInfo,
216                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
217   llvm_unreachable("should not be called");
218 }
219 
CC_MipsO32_FP64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)220 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
221                             CCValAssign::LocInfo LocInfo,
222                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
223   llvm_unreachable("should not be called");
224 }
225 
226 #include "MipsGenCallingConv.inc"
227 
CCAssignFnForCall(CallingConv::ID CC) const228 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
229   return CC_MipsO32;
230 }
231 
emitLogicalOp(unsigned ISDOpc,MVT RetVT,const Value * LHS,const Value * RHS)232 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
233                                      const Value *LHS, const Value *RHS) {
234   // Canonicalize immediates to the RHS first.
235   if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
236     std::swap(LHS, RHS);
237 
238   unsigned Opc;
239   switch (ISDOpc) {
240   case ISD::AND:
241     Opc = Mips::AND;
242     break;
243   case ISD::OR:
244     Opc = Mips::OR;
245     break;
246   case ISD::XOR:
247     Opc = Mips::XOR;
248     break;
249   default:
250     llvm_unreachable("unexpected opcode");
251   }
252 
253   unsigned LHSReg = getRegForValue(LHS);
254   if (!LHSReg)
255     return 0;
256 
257   unsigned RHSReg;
258   if (const auto *C = dyn_cast<ConstantInt>(RHS))
259     RHSReg = materializeInt(C, MVT::i32);
260   else
261     RHSReg = getRegForValue(RHS);
262   if (!RHSReg)
263     return 0;
264 
265   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
266   if (!ResultReg)
267     return 0;
268 
269   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
270   return ResultReg;
271 }
272 
fastMaterializeAlloca(const AllocaInst * AI)273 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
274   if (!TargetSupported)
275     return 0;
276 
277   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
278          "Alloca should always return a pointer.");
279 
280   DenseMap<const AllocaInst *, int>::iterator SI =
281       FuncInfo.StaticAllocaMap.find(AI);
282 
283   if (SI != FuncInfo.StaticAllocaMap.end()) {
284     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
285     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
286             ResultReg)
287         .addFrameIndex(SI->second)
288         .addImm(0);
289     return ResultReg;
290   }
291 
292   return 0;
293 }
294 
materializeInt(const Constant * C,MVT VT)295 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
296   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
297     return 0;
298   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
299   const ConstantInt *CI = cast<ConstantInt>(C);
300   return materialize32BitInt(CI->getZExtValue(), RC);
301 }
302 
materialize32BitInt(int64_t Imm,const TargetRegisterClass * RC)303 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
304                                            const TargetRegisterClass *RC) {
305   unsigned ResultReg = createResultReg(RC);
306 
307   if (isInt<16>(Imm)) {
308     unsigned Opc = Mips::ADDiu;
309     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
310     return ResultReg;
311   } else if (isUInt<16>(Imm)) {
312     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
313     return ResultReg;
314   }
315   unsigned Lo = Imm & 0xFFFF;
316   unsigned Hi = (Imm >> 16) & 0xFFFF;
317   if (Lo) {
318     // Both Lo and Hi have nonzero bits.
319     unsigned TmpReg = createResultReg(RC);
320     emitInst(Mips::LUi, TmpReg).addImm(Hi);
321     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
322   } else {
323     emitInst(Mips::LUi, ResultReg).addImm(Hi);
324   }
325   return ResultReg;
326 }
327 
materializeFP(const ConstantFP * CFP,MVT VT)328 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
329   if (UnsupportedFPMode)
330     return 0;
331   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
332   if (VT == MVT::f32) {
333     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
334     unsigned DestReg = createResultReg(RC);
335     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
336     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
337     return DestReg;
338   } else if (VT == MVT::f64) {
339     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
340     unsigned DestReg = createResultReg(RC);
341     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
342     unsigned TempReg2 =
343         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
344     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
345     return DestReg;
346   }
347   return 0;
348 }
349 
materializeGV(const GlobalValue * GV,MVT VT)350 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
351   // For now 32-bit only.
352   if (VT != MVT::i32)
353     return 0;
354   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
355   unsigned DestReg = createResultReg(RC);
356   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
357   bool IsThreadLocal = GVar && GVar->isThreadLocal();
358   // TLS not supported at this time.
359   if (IsThreadLocal)
360     return 0;
361   emitInst(Mips::LW, DestReg)
362       .addReg(MFI->getGlobalBaseReg())
363       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
364   if ((GV->hasInternalLinkage() ||
365        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
366     unsigned TempReg = createResultReg(RC);
367     emitInst(Mips::ADDiu, TempReg)
368         .addReg(DestReg)
369         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
370     DestReg = TempReg;
371   }
372   return DestReg;
373 }
374 
materializeExternalCallSym(MCSymbol * Sym)375 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
376   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
377   unsigned DestReg = createResultReg(RC);
378   emitInst(Mips::LW, DestReg)
379       .addReg(MFI->getGlobalBaseReg())
380       .addSym(Sym, MipsII::MO_GOT);
381   return DestReg;
382 }
383 
384 // Materialize a constant into a register, and return the register
385 // number (or zero if we failed to handle it).
fastMaterializeConstant(const Constant * C)386 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
387   if (!TargetSupported)
388     return 0;
389 
390   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
391 
392   // Only handle simple types.
393   if (!CEVT.isSimple())
394     return 0;
395   MVT VT = CEVT.getSimpleVT();
396 
397   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
398     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
399   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
400     return materializeGV(GV, VT);
401   else if (isa<ConstantInt>(C))
402     return materializeInt(C, VT);
403 
404   return 0;
405 }
406 
computeAddress(const Value * Obj,Address & Addr)407 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
408 
409   const User *U = nullptr;
410   unsigned Opcode = Instruction::UserOp1;
411   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
412     // Don't walk into other basic blocks unless the object is an alloca from
413     // another block, otherwise it may not have a virtual register assigned.
414     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
415         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
416       Opcode = I->getOpcode();
417       U = I;
418     }
419   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
420     Opcode = C->getOpcode();
421     U = C;
422   }
423   switch (Opcode) {
424   default:
425     break;
426   case Instruction::BitCast: {
427     // Look through bitcasts.
428     return computeAddress(U->getOperand(0), Addr);
429   }
430   case Instruction::GetElementPtr: {
431     Address SavedAddr = Addr;
432     uint64_t TmpOffset = Addr.getOffset();
433     // Iterate through the GEP folding the constants into offsets where
434     // we can.
435     gep_type_iterator GTI = gep_type_begin(U);
436     for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
437          ++i, ++GTI) {
438       const Value *Op = *i;
439       if (StructType *STy = dyn_cast<StructType>(*GTI)) {
440         const StructLayout *SL = DL.getStructLayout(STy);
441         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
442         TmpOffset += SL->getElementOffset(Idx);
443       } else {
444         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
445         for (;;) {
446           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
447             // Constant-offset addressing.
448             TmpOffset += CI->getSExtValue() * S;
449             break;
450           }
451           if (canFoldAddIntoGEP(U, Op)) {
452             // A compatible add with a constant operand. Fold the constant.
453             ConstantInt *CI =
454                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
455             TmpOffset += CI->getSExtValue() * S;
456             // Iterate on the other operand.
457             Op = cast<AddOperator>(Op)->getOperand(0);
458             continue;
459           }
460           // Unsupported
461           goto unsupported_gep;
462         }
463       }
464     }
465     // Try to grab the base operand now.
466     Addr.setOffset(TmpOffset);
467     if (computeAddress(U->getOperand(0), Addr))
468       return true;
469     // We failed, restore everything and try the other options.
470     Addr = SavedAddr;
471   unsupported_gep:
472     break;
473   }
474   case Instruction::Alloca: {
475     const AllocaInst *AI = cast<AllocaInst>(Obj);
476     DenseMap<const AllocaInst *, int>::iterator SI =
477         FuncInfo.StaticAllocaMap.find(AI);
478     if (SI != FuncInfo.StaticAllocaMap.end()) {
479       Addr.setKind(Address::FrameIndexBase);
480       Addr.setFI(SI->second);
481       return true;
482     }
483     break;
484   }
485   }
486   Addr.setReg(getRegForValue(Obj));
487   return Addr.getReg() != 0;
488 }
489 
computeCallAddress(const Value * V,Address & Addr)490 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
491   const User *U = nullptr;
492   unsigned Opcode = Instruction::UserOp1;
493 
494   if (const auto *I = dyn_cast<Instruction>(V)) {
495     // Check if the value is defined in the same basic block. This information
496     // is crucial to know whether or not folding an operand is valid.
497     if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
498       Opcode = I->getOpcode();
499       U = I;
500     }
501   } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
502     Opcode = C->getOpcode();
503     U = C;
504   }
505 
506   switch (Opcode) {
507   default:
508     break;
509   case Instruction::BitCast:
510     // Look past bitcasts if its operand is in the same BB.
511       return computeCallAddress(U->getOperand(0), Addr);
512     break;
513   case Instruction::IntToPtr:
514     // Look past no-op inttoptrs if its operand is in the same BB.
515     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
516         TLI.getPointerTy(DL))
517       return computeCallAddress(U->getOperand(0), Addr);
518     break;
519   case Instruction::PtrToInt:
520     // Look past no-op ptrtoints if its operand is in the same BB.
521     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
522       return computeCallAddress(U->getOperand(0), Addr);
523     break;
524   }
525 
526   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
527     Addr.setGlobalValue(GV);
528     return true;
529   }
530 
531   // If all else fails, try to materialize the value in a register.
532   if (!Addr.getGlobalValue()) {
533     Addr.setReg(getRegForValue(V));
534     return Addr.getReg() != 0;
535   }
536 
537   return false;
538 }
539 
isTypeLegal(Type * Ty,MVT & VT)540 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
541   EVT evt = TLI.getValueType(DL, Ty, true);
542   // Only handle simple types.
543   if (evt == MVT::Other || !evt.isSimple())
544     return false;
545   VT = evt.getSimpleVT();
546 
547   // Handle all legal types, i.e. a register that will directly hold this
548   // value.
549   return TLI.isTypeLegal(VT);
550 }
551 
isTypeSupported(Type * Ty,MVT & VT)552 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
553   if (Ty->isVectorTy())
554     return false;
555 
556   if (isTypeLegal(Ty, VT))
557     return true;
558 
559   // If this is a type than can be sign or zero-extended to a basic operation
560   // go ahead and accept it now.
561   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
562     return true;
563 
564   return false;
565 }
566 
isLoadTypeLegal(Type * Ty,MVT & VT)567 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
568   if (isTypeLegal(Ty, VT))
569     return true;
570   // We will extend this in a later patch:
571   //   If this is a type than can be sign or zero-extended to a basic operation
572   //   go ahead and accept it now.
573   if (VT == MVT::i8 || VT == MVT::i16)
574     return true;
575   return false;
576 }
577 // Because of how EmitCmp is called with fast-isel, you can
578 // end up with redundant "andi" instructions after the sequences emitted below.
579 // We should try and solve this issue in the future.
580 //
emitCmp(unsigned ResultReg,const CmpInst * CI)581 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
582   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
583   bool IsUnsigned = CI->isUnsigned();
584   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
585   if (LeftReg == 0)
586     return false;
587   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
588   if (RightReg == 0)
589     return false;
590   CmpInst::Predicate P = CI->getPredicate();
591 
592   switch (P) {
593   default:
594     return false;
595   case CmpInst::ICMP_EQ: {
596     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
597     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
598     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
599     break;
600   }
601   case CmpInst::ICMP_NE: {
602     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
603     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
604     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
605     break;
606   }
607   case CmpInst::ICMP_UGT: {
608     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
609     break;
610   }
611   case CmpInst::ICMP_ULT: {
612     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
613     break;
614   }
615   case CmpInst::ICMP_UGE: {
616     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
617     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
618     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
619     break;
620   }
621   case CmpInst::ICMP_ULE: {
622     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
623     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
624     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
625     break;
626   }
627   case CmpInst::ICMP_SGT: {
628     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
629     break;
630   }
631   case CmpInst::ICMP_SLT: {
632     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
633     break;
634   }
635   case CmpInst::ICMP_SGE: {
636     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
637     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
638     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
639     break;
640   }
641   case CmpInst::ICMP_SLE: {
642     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
643     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
644     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
645     break;
646   }
647   case CmpInst::FCMP_OEQ:
648   case CmpInst::FCMP_UNE:
649   case CmpInst::FCMP_OLT:
650   case CmpInst::FCMP_OLE:
651   case CmpInst::FCMP_OGT:
652   case CmpInst::FCMP_OGE: {
653     if (UnsupportedFPMode)
654       return false;
655     bool IsFloat = Left->getType()->isFloatTy();
656     bool IsDouble = Left->getType()->isDoubleTy();
657     if (!IsFloat && !IsDouble)
658       return false;
659     unsigned Opc, CondMovOpc;
660     switch (P) {
661     case CmpInst::FCMP_OEQ:
662       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
663       CondMovOpc = Mips::MOVT_I;
664       break;
665     case CmpInst::FCMP_UNE:
666       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
667       CondMovOpc = Mips::MOVF_I;
668       break;
669     case CmpInst::FCMP_OLT:
670       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
671       CondMovOpc = Mips::MOVT_I;
672       break;
673     case CmpInst::FCMP_OLE:
674       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
675       CondMovOpc = Mips::MOVT_I;
676       break;
677     case CmpInst::FCMP_OGT:
678       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
679       CondMovOpc = Mips::MOVF_I;
680       break;
681     case CmpInst::FCMP_OGE:
682       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
683       CondMovOpc = Mips::MOVF_I;
684       break;
685     default:
686       llvm_unreachable("Only switching of a subset of CCs.");
687     }
688     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
689     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
690     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
691     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
692     emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
693         Mips::FCC0, RegState::ImplicitDefine);
694     MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
695                                  .addReg(RegWithOne)
696                                  .addReg(Mips::FCC0)
697                                  .addReg(RegWithZero, RegState::Implicit);
698     MI->tieOperands(0, 3);
699     break;
700   }
701   }
702   return true;
703 }
emitLoad(MVT VT,unsigned & ResultReg,Address & Addr,unsigned Alignment)704 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
705                             unsigned Alignment) {
706   //
707   // more cases will be handled here in following patches.
708   //
709   unsigned Opc;
710   switch (VT.SimpleTy) {
711   case MVT::i32: {
712     ResultReg = createResultReg(&Mips::GPR32RegClass);
713     Opc = Mips::LW;
714     break;
715   }
716   case MVT::i16: {
717     ResultReg = createResultReg(&Mips::GPR32RegClass);
718     Opc = Mips::LHu;
719     break;
720   }
721   case MVT::i8: {
722     ResultReg = createResultReg(&Mips::GPR32RegClass);
723     Opc = Mips::LBu;
724     break;
725   }
726   case MVT::f32: {
727     if (UnsupportedFPMode)
728       return false;
729     ResultReg = createResultReg(&Mips::FGR32RegClass);
730     Opc = Mips::LWC1;
731     break;
732   }
733   case MVT::f64: {
734     if (UnsupportedFPMode)
735       return false;
736     ResultReg = createResultReg(&Mips::AFGR64RegClass);
737     Opc = Mips::LDC1;
738     break;
739   }
740   default:
741     return false;
742   }
743   if (Addr.isRegBase()) {
744     simplifyAddress(Addr);
745     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
746     return true;
747   }
748   if (Addr.isFIBase()) {
749     unsigned FI = Addr.getFI();
750     unsigned Align = 4;
751     unsigned Offset = Addr.getOffset();
752     MachineFrameInfo &MFI = *MF->getFrameInfo();
753     MachineMemOperand *MMO = MF->getMachineMemOperand(
754         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
755         MFI.getObjectSize(FI), Align);
756     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
757         .addFrameIndex(FI)
758         .addImm(Offset)
759         .addMemOperand(MMO);
760     return true;
761   }
762   return false;
763 }
764 
emitStore(MVT VT,unsigned SrcReg,Address & Addr,unsigned Alignment)765 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
766                              unsigned Alignment) {
767   //
768   // more cases will be handled here in following patches.
769   //
770   unsigned Opc;
771   switch (VT.SimpleTy) {
772   case MVT::i8:
773     Opc = Mips::SB;
774     break;
775   case MVT::i16:
776     Opc = Mips::SH;
777     break;
778   case MVT::i32:
779     Opc = Mips::SW;
780     break;
781   case MVT::f32:
782     if (UnsupportedFPMode)
783       return false;
784     Opc = Mips::SWC1;
785     break;
786   case MVT::f64:
787     if (UnsupportedFPMode)
788       return false;
789     Opc = Mips::SDC1;
790     break;
791   default:
792     return false;
793   }
794   if (Addr.isRegBase()) {
795     simplifyAddress(Addr);
796     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
797     return true;
798   }
799   if (Addr.isFIBase()) {
800     unsigned FI = Addr.getFI();
801     unsigned Align = 4;
802     unsigned Offset = Addr.getOffset();
803     MachineFrameInfo &MFI = *MF->getFrameInfo();
804     MachineMemOperand *MMO = MF->getMachineMemOperand(
805         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
806         MFI.getObjectSize(FI), Align);
807     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
808         .addReg(SrcReg)
809         .addFrameIndex(FI)
810         .addImm(Offset)
811         .addMemOperand(MMO);
812     return true;
813   }
814   return false;
815 }
816 
selectLogicalOp(const Instruction * I)817 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
818   MVT VT;
819   if (!isTypeSupported(I->getType(), VT))
820     return false;
821 
822   unsigned ResultReg;
823   switch (I->getOpcode()) {
824   default:
825     llvm_unreachable("Unexpected instruction.");
826   case Instruction::And:
827     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
828     break;
829   case Instruction::Or:
830     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
831     break;
832   case Instruction::Xor:
833     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
834     break;
835   }
836 
837   if (!ResultReg)
838     return false;
839 
840   updateValueMap(I, ResultReg);
841   return true;
842 }
843 
selectLoad(const Instruction * I)844 bool MipsFastISel::selectLoad(const Instruction *I) {
845   // Atomic loads need special handling.
846   if (cast<LoadInst>(I)->isAtomic())
847     return false;
848 
849   // Verify we have a legal type before going any further.
850   MVT VT;
851   if (!isLoadTypeLegal(I->getType(), VT))
852     return false;
853 
854   // See if we can handle this address.
855   Address Addr;
856   if (!computeAddress(I->getOperand(0), Addr))
857     return false;
858 
859   unsigned ResultReg;
860   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
861     return false;
862   updateValueMap(I, ResultReg);
863   return true;
864 }
865 
selectStore(const Instruction * I)866 bool MipsFastISel::selectStore(const Instruction *I) {
867   Value *Op0 = I->getOperand(0);
868   unsigned SrcReg = 0;
869 
870   // Atomic stores need special handling.
871   if (cast<StoreInst>(I)->isAtomic())
872     return false;
873 
874   // Verify we have a legal type before going any further.
875   MVT VT;
876   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
877     return false;
878 
879   // Get the value to be stored into a register.
880   SrcReg = getRegForValue(Op0);
881   if (SrcReg == 0)
882     return false;
883 
884   // See if we can handle this address.
885   Address Addr;
886   if (!computeAddress(I->getOperand(1), Addr))
887     return false;
888 
889   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
890     return false;
891   return true;
892 }
893 
894 //
895 // This can cause a redundant sltiu to be generated.
896 // FIXME: try and eliminate this in a future patch.
897 //
selectBranch(const Instruction * I)898 bool MipsFastISel::selectBranch(const Instruction *I) {
899   const BranchInst *BI = cast<BranchInst>(I);
900   MachineBasicBlock *BrBB = FuncInfo.MBB;
901   //
902   // TBB is the basic block for the case where the comparison is true.
903   // FBB is the basic block for the case where the comparison is false.
904   // if (cond) goto TBB
905   // goto FBB
906   // TBB:
907   //
908   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
909   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
910   BI->getCondition();
911   // For now, just try the simplest case where it's fed by a compare.
912   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
913     unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
914     if (!emitCmp(CondReg, CI))
915       return false;
916     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
917         .addReg(CondReg)
918         .addMBB(TBB);
919     finishCondBranch(BI->getParent(), TBB, FBB);
920     return true;
921   }
922   return false;
923 }
924 
selectCmp(const Instruction * I)925 bool MipsFastISel::selectCmp(const Instruction *I) {
926   const CmpInst *CI = cast<CmpInst>(I);
927   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
928   if (!emitCmp(ResultReg, CI))
929     return false;
930   updateValueMap(I, ResultReg);
931   return true;
932 }
933 
934 // Attempt to fast-select a floating-point extend instruction.
selectFPExt(const Instruction * I)935 bool MipsFastISel::selectFPExt(const Instruction *I) {
936   if (UnsupportedFPMode)
937     return false;
938   Value *Src = I->getOperand(0);
939   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
940   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
941 
942   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
943     return false;
944 
945   unsigned SrcReg =
946       getRegForValue(Src); // his must be a 32 bit floating point register class
947                            // maybe we should handle this differently
948   if (!SrcReg)
949     return false;
950 
951   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
952   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
953   updateValueMap(I, DestReg);
954   return true;
955 }
956 
selectSelect(const Instruction * I)957 bool MipsFastISel::selectSelect(const Instruction *I) {
958   assert(isa<SelectInst>(I) && "Expected a select instruction.");
959 
960   MVT VT;
961   if (!isTypeSupported(I->getType(), VT))
962     return false;
963 
964   unsigned CondMovOpc;
965   const TargetRegisterClass *RC;
966 
967   if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
968     CondMovOpc = Mips::MOVN_I_I;
969     RC = &Mips::GPR32RegClass;
970   } else if (VT == MVT::f32) {
971     CondMovOpc = Mips::MOVN_I_S;
972     RC = &Mips::FGR32RegClass;
973   } else if (VT == MVT::f64) {
974     CondMovOpc = Mips::MOVN_I_D32;
975     RC = &Mips::AFGR64RegClass;
976   } else
977     return false;
978 
979   const SelectInst *SI = cast<SelectInst>(I);
980   const Value *Cond = SI->getCondition();
981   unsigned Src1Reg = getRegForValue(SI->getTrueValue());
982   unsigned Src2Reg = getRegForValue(SI->getFalseValue());
983   unsigned CondReg = getRegForValue(Cond);
984 
985   if (!Src1Reg || !Src2Reg || !CondReg)
986     return false;
987 
988   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
989   if (!ZExtCondReg)
990     return false;
991 
992   if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
993     return false;
994 
995   unsigned ResultReg = createResultReg(RC);
996   unsigned TempReg = createResultReg(RC);
997 
998   if (!ResultReg || !TempReg)
999     return false;
1000 
1001   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1002   emitInst(CondMovOpc, ResultReg)
1003     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1004   updateValueMap(I, ResultReg);
1005   return true;
1006 }
1007 
1008 // Attempt to fast-select a floating-point truncate instruction.
selectFPTrunc(const Instruction * I)1009 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1010   if (UnsupportedFPMode)
1011     return false;
1012   Value *Src = I->getOperand(0);
1013   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1014   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1015 
1016   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1017     return false;
1018 
1019   unsigned SrcReg = getRegForValue(Src);
1020   if (!SrcReg)
1021     return false;
1022 
1023   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1024   if (!DestReg)
1025     return false;
1026 
1027   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1028   updateValueMap(I, DestReg);
1029   return true;
1030 }
1031 
1032 // Attempt to fast-select a floating-point-to-integer conversion.
selectFPToInt(const Instruction * I,bool IsSigned)1033 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1034   if (UnsupportedFPMode)
1035     return false;
1036   MVT DstVT, SrcVT;
1037   if (!IsSigned)
1038     return false; // We don't handle this case yet. There is no native
1039                   // instruction for this but it can be synthesized.
1040   Type *DstTy = I->getType();
1041   if (!isTypeLegal(DstTy, DstVT))
1042     return false;
1043 
1044   if (DstVT != MVT::i32)
1045     return false;
1046 
1047   Value *Src = I->getOperand(0);
1048   Type *SrcTy = Src->getType();
1049   if (!isTypeLegal(SrcTy, SrcVT))
1050     return false;
1051 
1052   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1053     return false;
1054 
1055   unsigned SrcReg = getRegForValue(Src);
1056   if (SrcReg == 0)
1057     return false;
1058 
1059   // Determine the opcode for the conversion, which takes place
1060   // entirely within FPRs.
1061   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1062   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1063   unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1064 
1065   // Generate the convert.
1066   emitInst(Opc, TempReg).addReg(SrcReg);
1067   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1068 
1069   updateValueMap(I, DestReg);
1070   return true;
1071 }
1072 
processCallArgs(CallLoweringInfo & CLI,SmallVectorImpl<MVT> & OutVTs,unsigned & NumBytes)1073 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1074                                    SmallVectorImpl<MVT> &OutVTs,
1075                                    unsigned &NumBytes) {
1076   CallingConv::ID CC = CLI.CallConv;
1077   SmallVector<CCValAssign, 16> ArgLocs;
1078   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1079   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1080   // Get a count of how many bytes are to be pushed on the stack.
1081   NumBytes = CCInfo.getNextStackOffset();
1082   // This is the minimum argument area used for A0-A3.
1083   if (NumBytes < 16)
1084     NumBytes = 16;
1085 
1086   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1087   // Process the args.
1088   MVT firstMVT;
1089   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1090     CCValAssign &VA = ArgLocs[i];
1091     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1092     MVT ArgVT = OutVTs[VA.getValNo()];
1093 
1094     if (i == 0) {
1095       firstMVT = ArgVT;
1096       if (ArgVT == MVT::f32) {
1097         VA.convertToReg(Mips::F12);
1098       } else if (ArgVT == MVT::f64) {
1099         VA.convertToReg(Mips::D6);
1100       }
1101     } else if (i == 1) {
1102       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1103         if (ArgVT == MVT::f32) {
1104           VA.convertToReg(Mips::F14);
1105         } else if (ArgVT == MVT::f64) {
1106           VA.convertToReg(Mips::D7);
1107         }
1108       }
1109     }
1110     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1111          (ArgVT == MVT::i8)) &&
1112         VA.isMemLoc()) {
1113       switch (VA.getLocMemOffset()) {
1114       case 0:
1115         VA.convertToReg(Mips::A0);
1116         break;
1117       case 4:
1118         VA.convertToReg(Mips::A1);
1119         break;
1120       case 8:
1121         VA.convertToReg(Mips::A2);
1122         break;
1123       case 12:
1124         VA.convertToReg(Mips::A3);
1125         break;
1126       default:
1127         break;
1128       }
1129     }
1130     unsigned ArgReg = getRegForValue(ArgVal);
1131     if (!ArgReg)
1132       return false;
1133 
1134     // Handle arg promotion: SExt, ZExt, AExt.
1135     switch (VA.getLocInfo()) {
1136     case CCValAssign::Full:
1137       break;
1138     case CCValAssign::AExt:
1139     case CCValAssign::SExt: {
1140       MVT DestVT = VA.getLocVT();
1141       MVT SrcVT = ArgVT;
1142       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1143       if (!ArgReg)
1144         return false;
1145       break;
1146     }
1147     case CCValAssign::ZExt: {
1148       MVT DestVT = VA.getLocVT();
1149       MVT SrcVT = ArgVT;
1150       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1151       if (!ArgReg)
1152         return false;
1153       break;
1154     }
1155     default:
1156       llvm_unreachable("Unknown arg promotion!");
1157     }
1158 
1159     // Now copy/store arg to correct locations.
1160     if (VA.isRegLoc() && !VA.needsCustom()) {
1161       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1162               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1163       CLI.OutRegs.push_back(VA.getLocReg());
1164     } else if (VA.needsCustom()) {
1165       llvm_unreachable("Mips does not use custom args.");
1166       return false;
1167     } else {
1168       //
1169       // FIXME: This path will currently return false. It was copied
1170       // from the AArch64 port and should be essentially fine for Mips too.
1171       // The work to finish up this path will be done in a follow-on patch.
1172       //
1173       assert(VA.isMemLoc() && "Assuming store on stack.");
1174       // Don't emit stores for undef values.
1175       if (isa<UndefValue>(ArgVal))
1176         continue;
1177 
1178       // Need to store on the stack.
1179       // FIXME: This alignment is incorrect but this path is disabled
1180       // for now (will return false). We need to determine the right alignment
1181       // based on the normal alignment for the underlying machine type.
1182       //
1183       unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1184 
1185       unsigned BEAlign = 0;
1186       if (ArgSize < 8 && !Subtarget->isLittle())
1187         BEAlign = 8 - ArgSize;
1188 
1189       Address Addr;
1190       Addr.setKind(Address::RegBase);
1191       Addr.setReg(Mips::SP);
1192       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1193 
1194       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1195       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1196           MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1197           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1198       (void)(MMO);
1199       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1200       return false; // can't store on the stack yet.
1201     }
1202   }
1203 
1204   return true;
1205 }
1206 
finishCall(CallLoweringInfo & CLI,MVT RetVT,unsigned NumBytes)1207 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1208                               unsigned NumBytes) {
1209   CallingConv::ID CC = CLI.CallConv;
1210   emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1211   if (RetVT != MVT::isVoid) {
1212     SmallVector<CCValAssign, 16> RVLocs;
1213     CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1214     CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1215 
1216     // Only handle a single return value.
1217     if (RVLocs.size() != 1)
1218       return false;
1219     // Copy all of the result registers out of their specified physreg.
1220     MVT CopyVT = RVLocs[0].getValVT();
1221     // Special handling for extended integers.
1222     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1223       CopyVT = MVT::i32;
1224 
1225     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1226     if (!ResultReg)
1227       return false;
1228     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1229             TII.get(TargetOpcode::COPY),
1230             ResultReg).addReg(RVLocs[0].getLocReg());
1231     CLI.InRegs.push_back(RVLocs[0].getLocReg());
1232 
1233     CLI.ResultReg = ResultReg;
1234     CLI.NumResultRegs = 1;
1235   }
1236   return true;
1237 }
1238 
fastLowerCall(CallLoweringInfo & CLI)1239 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1240   if (!TargetSupported)
1241     return false;
1242 
1243   CallingConv::ID CC = CLI.CallConv;
1244   bool IsTailCall = CLI.IsTailCall;
1245   bool IsVarArg = CLI.IsVarArg;
1246   const Value *Callee = CLI.Callee;
1247   MCSymbol *Symbol = CLI.Symbol;
1248 
1249   // Do not handle FastCC.
1250   if (CC == CallingConv::Fast)
1251     return false;
1252 
1253   // Allow SelectionDAG isel to handle tail calls.
1254   if (IsTailCall)
1255     return false;
1256 
1257   // Let SDISel handle vararg functions.
1258   if (IsVarArg)
1259     return false;
1260 
1261   // FIXME: Only handle *simple* calls for now.
1262   MVT RetVT;
1263   if (CLI.RetTy->isVoidTy())
1264     RetVT = MVT::isVoid;
1265   else if (!isTypeSupported(CLI.RetTy, RetVT))
1266     return false;
1267 
1268   for (auto Flag : CLI.OutFlags)
1269     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1270       return false;
1271 
1272   // Set up the argument vectors.
1273   SmallVector<MVT, 16> OutVTs;
1274   OutVTs.reserve(CLI.OutVals.size());
1275 
1276   for (auto *Val : CLI.OutVals) {
1277     MVT VT;
1278     if (!isTypeLegal(Val->getType(), VT) &&
1279         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1280       return false;
1281 
1282     // We don't handle vector parameters yet.
1283     if (VT.isVector() || VT.getSizeInBits() > 64)
1284       return false;
1285 
1286     OutVTs.push_back(VT);
1287   }
1288 
1289   Address Addr;
1290   if (!computeCallAddress(Callee, Addr))
1291     return false;
1292 
1293   // Handle the arguments now that we've gotten them.
1294   unsigned NumBytes;
1295   if (!processCallArgs(CLI, OutVTs, NumBytes))
1296     return false;
1297 
1298   if (!Addr.getGlobalValue())
1299     return false;
1300 
1301   // Issue the call.
1302   unsigned DestAddress;
1303   if (Symbol)
1304     DestAddress = materializeExternalCallSym(Symbol);
1305   else
1306     DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1307   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1308   MachineInstrBuilder MIB =
1309       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1310               Mips::RA).addReg(Mips::T9);
1311 
1312   // Add implicit physical register uses to the call.
1313   for (auto Reg : CLI.OutRegs)
1314     MIB.addReg(Reg, RegState::Implicit);
1315 
1316   // Add a register mask with the call-preserved registers.
1317   // Proper defs for return values will be added by setPhysRegsDeadExcept().
1318   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1319 
1320   CLI.Call = MIB;
1321 
1322   // Finish off the call including any return values.
1323   return finishCall(CLI, RetVT, NumBytes);
1324 }
1325 
fastLowerIntrinsicCall(const IntrinsicInst * II)1326 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1327   if (!TargetSupported)
1328     return false;
1329 
1330   switch (II->getIntrinsicID()) {
1331   default:
1332     return false;
1333   case Intrinsic::bswap: {
1334     Type *RetTy = II->getCalledFunction()->getReturnType();
1335 
1336     MVT VT;
1337     if (!isTypeSupported(RetTy, VT))
1338       return false;
1339 
1340     unsigned SrcReg = getRegForValue(II->getOperand(0));
1341     if (SrcReg == 0)
1342       return false;
1343     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1344     if (DestReg == 0)
1345       return false;
1346     if (VT == MVT::i16) {
1347       if (Subtarget->hasMips32r2()) {
1348         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1349         updateValueMap(II, DestReg);
1350         return true;
1351       } else {
1352         unsigned TempReg[3];
1353         for (int i = 0; i < 3; i++) {
1354           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1355           if (TempReg[i] == 0)
1356             return false;
1357         }
1358         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1359         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1360         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1361         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1362         updateValueMap(II, DestReg);
1363         return true;
1364       }
1365     } else if (VT == MVT::i32) {
1366       if (Subtarget->hasMips32r2()) {
1367         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1368         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1369         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1370         updateValueMap(II, DestReg);
1371         return true;
1372       } else {
1373         unsigned TempReg[8];
1374         for (int i = 0; i < 8; i++) {
1375           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1376           if (TempReg[i] == 0)
1377             return false;
1378         }
1379 
1380         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1381         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1382         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1383         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1384 
1385         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1386         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1387 
1388         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1389         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1390         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1391         updateValueMap(II, DestReg);
1392         return true;
1393       }
1394     }
1395     return false;
1396   }
1397   case Intrinsic::memcpy:
1398   case Intrinsic::memmove: {
1399     const auto *MTI = cast<MemTransferInst>(II);
1400     // Don't handle volatile.
1401     if (MTI->isVolatile())
1402       return false;
1403     if (!MTI->getLength()->getType()->isIntegerTy(32))
1404       return false;
1405     const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1406     return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1407   }
1408   case Intrinsic::memset: {
1409     const MemSetInst *MSI = cast<MemSetInst>(II);
1410     // Don't handle volatile.
1411     if (MSI->isVolatile())
1412       return false;
1413     if (!MSI->getLength()->getType()->isIntegerTy(32))
1414       return false;
1415     return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1416   }
1417   }
1418   return false;
1419 }
1420 
selectRet(const Instruction * I)1421 bool MipsFastISel::selectRet(const Instruction *I) {
1422   const Function &F = *I->getParent()->getParent();
1423   const ReturnInst *Ret = cast<ReturnInst>(I);
1424 
1425   if (!FuncInfo.CanLowerReturn)
1426     return false;
1427 
1428   // Build a list of return value registers.
1429   SmallVector<unsigned, 4> RetRegs;
1430 
1431   if (Ret->getNumOperands() > 0) {
1432     CallingConv::ID CC = F.getCallingConv();
1433 
1434     // Do not handle FastCC.
1435     if (CC == CallingConv::Fast)
1436       return false;
1437 
1438     SmallVector<ISD::OutputArg, 4> Outs;
1439     GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1440 
1441     // Analyze operands of the call, assigning locations to each operand.
1442     SmallVector<CCValAssign, 16> ValLocs;
1443     MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1444                        I->getContext());
1445     CCAssignFn *RetCC = RetCC_Mips;
1446     CCInfo.AnalyzeReturn(Outs, RetCC);
1447 
1448     // Only handle a single return value for now.
1449     if (ValLocs.size() != 1)
1450       return false;
1451 
1452     CCValAssign &VA = ValLocs[0];
1453     const Value *RV = Ret->getOperand(0);
1454 
1455     // Don't bother handling odd stuff for now.
1456     if ((VA.getLocInfo() != CCValAssign::Full) &&
1457         (VA.getLocInfo() != CCValAssign::BCvt))
1458       return false;
1459 
1460     // Only handle register returns for now.
1461     if (!VA.isRegLoc())
1462       return false;
1463 
1464     unsigned Reg = getRegForValue(RV);
1465     if (Reg == 0)
1466       return false;
1467 
1468     unsigned SrcReg = Reg + VA.getValNo();
1469     unsigned DestReg = VA.getLocReg();
1470     // Avoid a cross-class copy. This is very unlikely.
1471     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1472       return false;
1473 
1474     EVT RVEVT = TLI.getValueType(DL, RV->getType());
1475     if (!RVEVT.isSimple())
1476       return false;
1477 
1478     if (RVEVT.isVector())
1479       return false;
1480 
1481     MVT RVVT = RVEVT.getSimpleVT();
1482     if (RVVT == MVT::f128)
1483       return false;
1484 
1485     MVT DestVT = VA.getValVT();
1486     // Special handling for extended integers.
1487     if (RVVT != DestVT) {
1488       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1489         return false;
1490 
1491       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1492         bool IsZExt = Outs[0].Flags.isZExt();
1493         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1494         if (SrcReg == 0)
1495           return false;
1496       }
1497     }
1498 
1499     // Make the copy.
1500     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1501             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1502 
1503     // Add register to return instruction.
1504     RetRegs.push_back(VA.getLocReg());
1505   }
1506   MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1507   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1508     MIB.addReg(RetRegs[i], RegState::Implicit);
1509   return true;
1510 }
1511 
selectTrunc(const Instruction * I)1512 bool MipsFastISel::selectTrunc(const Instruction *I) {
1513   // The high bits for a type smaller than the register size are assumed to be
1514   // undefined.
1515   Value *Op = I->getOperand(0);
1516 
1517   EVT SrcVT, DestVT;
1518   SrcVT = TLI.getValueType(DL, Op->getType(), true);
1519   DestVT = TLI.getValueType(DL, I->getType(), true);
1520 
1521   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1522     return false;
1523   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1524     return false;
1525 
1526   unsigned SrcReg = getRegForValue(Op);
1527   if (!SrcReg)
1528     return false;
1529 
1530   // Because the high bits are undefined, a truncate doesn't generate
1531   // any code.
1532   updateValueMap(I, SrcReg);
1533   return true;
1534 }
selectIntExt(const Instruction * I)1535 bool MipsFastISel::selectIntExt(const Instruction *I) {
1536   Type *DestTy = I->getType();
1537   Value *Src = I->getOperand(0);
1538   Type *SrcTy = Src->getType();
1539 
1540   bool isZExt = isa<ZExtInst>(I);
1541   unsigned SrcReg = getRegForValue(Src);
1542   if (!SrcReg)
1543     return false;
1544 
1545   EVT SrcEVT, DestEVT;
1546   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1547   DestEVT = TLI.getValueType(DL, DestTy, true);
1548   if (!SrcEVT.isSimple())
1549     return false;
1550   if (!DestEVT.isSimple())
1551     return false;
1552 
1553   MVT SrcVT = SrcEVT.getSimpleVT();
1554   MVT DestVT = DestEVT.getSimpleVT();
1555   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1556 
1557   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1558     return false;
1559   updateValueMap(I, ResultReg);
1560   return true;
1561 }
emitIntSExt32r1(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg)1562 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1563                                    unsigned DestReg) {
1564   unsigned ShiftAmt;
1565   switch (SrcVT.SimpleTy) {
1566   default:
1567     return false;
1568   case MVT::i8:
1569     ShiftAmt = 24;
1570     break;
1571   case MVT::i16:
1572     ShiftAmt = 16;
1573     break;
1574   }
1575   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1576   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1577   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1578   return true;
1579 }
1580 
emitIntSExt32r2(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg)1581 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1582                                    unsigned DestReg) {
1583   switch (SrcVT.SimpleTy) {
1584   default:
1585     return false;
1586   case MVT::i8:
1587     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1588     break;
1589   case MVT::i16:
1590     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1591     break;
1592   }
1593   return true;
1594 }
1595 
emitIntSExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg)1596 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1597                                unsigned DestReg) {
1598   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1599     return false;
1600   if (Subtarget->hasMips32r2())
1601     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1602   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1603 }
1604 
emitIntZExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg)1605 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1606                                unsigned DestReg) {
1607   int64_t Imm;
1608 
1609   switch (SrcVT.SimpleTy) {
1610   default:
1611     return false;
1612   case MVT::i1:
1613     Imm = 1;
1614     break;
1615   case MVT::i8:
1616     Imm = 0xff;
1617     break;
1618   case MVT::i16:
1619     Imm = 0xffff;
1620     break;
1621   }
1622 
1623   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1624   return true;
1625 }
1626 
emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt)1627 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1628                               unsigned DestReg, bool IsZExt) {
1629   // FastISel does not have plumbing to deal with extensions where the SrcVT or
1630   // DestVT are odd things, so test to make sure that they are both types we can
1631   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1632   // bail out to SelectionDAG.
1633   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1634       ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1635     return false;
1636   if (IsZExt)
1637     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1638   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1639 }
1640 
emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,bool isZExt)1641 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1642                                   bool isZExt) {
1643   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1644   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1645   return Success ? DestReg : 0;
1646 }
1647 
selectDivRem(const Instruction * I,unsigned ISDOpcode)1648 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1649   EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1650   if (!DestEVT.isSimple())
1651     return false;
1652 
1653   MVT DestVT = DestEVT.getSimpleVT();
1654   if (DestVT != MVT::i32)
1655     return false;
1656 
1657   unsigned DivOpc;
1658   switch (ISDOpcode) {
1659   default:
1660     return false;
1661   case ISD::SDIV:
1662   case ISD::SREM:
1663     DivOpc = Mips::SDIV;
1664     break;
1665   case ISD::UDIV:
1666   case ISD::UREM:
1667     DivOpc = Mips::UDIV;
1668     break;
1669   }
1670 
1671   unsigned Src0Reg = getRegForValue(I->getOperand(0));
1672   unsigned Src1Reg = getRegForValue(I->getOperand(1));
1673   if (!Src0Reg || !Src1Reg)
1674     return false;
1675 
1676   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1677   emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1678 
1679   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1680   if (!ResultReg)
1681     return false;
1682 
1683   unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1684                        ? Mips::MFHI
1685                        : Mips::MFLO;
1686   emitInst(MFOpc, ResultReg);
1687 
1688   updateValueMap(I, ResultReg);
1689   return true;
1690 }
1691 
selectShift(const Instruction * I)1692 bool MipsFastISel::selectShift(const Instruction *I) {
1693   MVT RetVT;
1694 
1695   if (!isTypeSupported(I->getType(), RetVT))
1696     return false;
1697 
1698   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1699   if (!ResultReg)
1700     return false;
1701 
1702   unsigned Opcode = I->getOpcode();
1703   const Value *Op0 = I->getOperand(0);
1704   unsigned Op0Reg = getRegForValue(Op0);
1705   if (!Op0Reg)
1706     return false;
1707 
1708   // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1709   if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1710     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1711     if (!TempReg)
1712       return false;
1713 
1714     MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1715     bool IsZExt = Opcode == Instruction::LShr;
1716     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1717       return false;
1718 
1719     Op0Reg = TempReg;
1720   }
1721 
1722   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1723     uint64_t ShiftVal = C->getZExtValue();
1724 
1725     switch (Opcode) {
1726     default:
1727       llvm_unreachable("Unexpected instruction.");
1728     case Instruction::Shl:
1729       Opcode = Mips::SLL;
1730       break;
1731     case Instruction::AShr:
1732       Opcode = Mips::SRA;
1733       break;
1734     case Instruction::LShr:
1735       Opcode = Mips::SRL;
1736       break;
1737     }
1738 
1739     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1740     updateValueMap(I, ResultReg);
1741     return true;
1742   }
1743 
1744   unsigned Op1Reg = getRegForValue(I->getOperand(1));
1745   if (!Op1Reg)
1746     return false;
1747 
1748   switch (Opcode) {
1749   default:
1750     llvm_unreachable("Unexpected instruction.");
1751   case Instruction::Shl:
1752     Opcode = Mips::SLLV;
1753     break;
1754   case Instruction::AShr:
1755     Opcode = Mips::SRAV;
1756     break;
1757   case Instruction::LShr:
1758     Opcode = Mips::SRLV;
1759     break;
1760   }
1761 
1762   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1763   updateValueMap(I, ResultReg);
1764   return true;
1765 }
1766 
fastSelectInstruction(const Instruction * I)1767 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1768   if (!TargetSupported)
1769     return false;
1770   switch (I->getOpcode()) {
1771   default:
1772     break;
1773   case Instruction::Load:
1774     return selectLoad(I);
1775   case Instruction::Store:
1776     return selectStore(I);
1777   case Instruction::SDiv:
1778     if (!selectBinaryOp(I, ISD::SDIV))
1779       return selectDivRem(I, ISD::SDIV);
1780     return true;
1781   case Instruction::UDiv:
1782     if (!selectBinaryOp(I, ISD::UDIV))
1783       return selectDivRem(I, ISD::UDIV);
1784     return true;
1785   case Instruction::SRem:
1786     if (!selectBinaryOp(I, ISD::SREM))
1787       return selectDivRem(I, ISD::SREM);
1788     return true;
1789   case Instruction::URem:
1790     if (!selectBinaryOp(I, ISD::UREM))
1791       return selectDivRem(I, ISD::UREM);
1792     return true;
1793   case Instruction::Shl:
1794   case Instruction::LShr:
1795   case Instruction::AShr:
1796     return selectShift(I);
1797   case Instruction::And:
1798   case Instruction::Or:
1799   case Instruction::Xor:
1800     return selectLogicalOp(I);
1801   case Instruction::Br:
1802     return selectBranch(I);
1803   case Instruction::Ret:
1804     return selectRet(I);
1805   case Instruction::Trunc:
1806     return selectTrunc(I);
1807   case Instruction::ZExt:
1808   case Instruction::SExt:
1809     return selectIntExt(I);
1810   case Instruction::FPTrunc:
1811     return selectFPTrunc(I);
1812   case Instruction::FPExt:
1813     return selectFPExt(I);
1814   case Instruction::FPToSI:
1815     return selectFPToInt(I, /*isSigned*/ true);
1816   case Instruction::FPToUI:
1817     return selectFPToInt(I, /*isSigned*/ false);
1818   case Instruction::ICmp:
1819   case Instruction::FCmp:
1820     return selectCmp(I);
1821   case Instruction::Select:
1822     return selectSelect(I);
1823   }
1824   return false;
1825 }
1826 
getRegEnsuringSimpleIntegerWidening(const Value * V,bool IsUnsigned)1827 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1828                                                            bool IsUnsigned) {
1829   unsigned VReg = getRegForValue(V);
1830   if (VReg == 0)
1831     return 0;
1832   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
1833   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1834     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1835     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1836       return 0;
1837     VReg = TempReg;
1838   }
1839   return VReg;
1840 }
1841 
simplifyAddress(Address & Addr)1842 void MipsFastISel::simplifyAddress(Address &Addr) {
1843   if (!isInt<16>(Addr.getOffset())) {
1844     unsigned TempReg =
1845         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1846     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1847     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1848     Addr.setReg(DestReg);
1849     Addr.setOffset(0);
1850   }
1851 }
1852 
fastEmitInst_rr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,unsigned Op1,bool Op1IsKill)1853 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1854                                        const TargetRegisterClass *RC,
1855                                        unsigned Op0, bool Op0IsKill,
1856                                        unsigned Op1, bool Op1IsKill) {
1857   // We treat the MUL instruction in a special way because it clobbers
1858   // the HI0 & LO0 registers. The TableGen definition of this instruction can
1859   // mark these registers only as implicitly defined. As a result, the
1860   // register allocator runs out of registers when this instruction is
1861   // followed by another instruction that defines the same registers too.
1862   // We can fix this by explicitly marking those registers as dead.
1863   if (MachineInstOpcode == Mips::MUL) {
1864     unsigned ResultReg = createResultReg(RC);
1865     const MCInstrDesc &II = TII.get(MachineInstOpcode);
1866     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1867     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1868     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1869       .addReg(Op0, getKillRegState(Op0IsKill))
1870       .addReg(Op1, getKillRegState(Op1IsKill))
1871       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1872       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1873     return ResultReg;
1874   }
1875 
1876   return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1877                                    Op1IsKill);
1878 }
1879 
1880 namespace llvm {
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo)1881 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1882                                const TargetLibraryInfo *libInfo) {
1883   return new MipsFastISel(funcInfo, libInfo);
1884 }
1885 }
1886