| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandPredSpillCode.cpp | 105 MachineOperand &Op4 = MI->getOperand(4); in runOnMachineFunction() local
114 NewMI->addOperand(Op4); in runOnMachineFunction()
147 MachineOperand &Op4 = MI->getOperand(4); // Modifier value. in runOnMachineFunction() local
151 Hexagon::C6)->addOperand(Op4); in runOnMachineFunction()
189 MachineOperand &Op4 = MI->getOperand(4); // Modifier value. in runOnMachineFunction() local
192 Hexagon::C6)->addOperand(Op4); in runOnMachineFunction()
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| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
| D | reduce.hpp | 157 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
162 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
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| /external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
| D | reduce.hpp | 71 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
75 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in blockReduce() argument
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in blockReduce()
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| /external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
| D | reduce.hpp | 168 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
173 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
| D | reduce.hpp | 186 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
191 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
207 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
211 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
|
| /external/opencv3/modules/cudaarithm/src/cuda/ |
| D | minmax_mat.cu | 114 template <class Op4>
123 gridTransformBinary(src1_, src2_, dst_, Op4(), stream); in minMaxMat_v4()
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/ |
| D | reduce.hpp | 69 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
73 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in warpReduce() argument
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in warpReduce()
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/ |
| D | reduce.hpp | 66 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
70 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in reduce() argument
75 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in reduce()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3874 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3876 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3878 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3895 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3907 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
3917 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3938 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
3940 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3942 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
3959 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1243 SDValue Op4 = Node->getOperand(4); in Select() local
1244 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 922 SDValue Op3, SDValue Op4);
924 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2988 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
3000 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
3009 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5405 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
5406 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
5410 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
5454 LastOp = &Op4; in tryConvertingToTwoOperandForm()
5475 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5773 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
5774 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
5780 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5781 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|