Searched refs:OpN (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 686 SDNode *OpN = Op.getNode(); in ScheduleNode() local
690 GluedOpN = OpN; in ScheduleNode()
691 assert(OpN->getNodeId() != 0 && "Glue operand not ready?"); in ScheduleNode()
692 OpN->setNodeId(0); in ScheduleNode()
693 ScheduleNode(OpN); in ScheduleNode()
697 if (OpN == GluedOpN) in ScheduleNode()
701 DenseMap<SDNode*, SDNode*>::iterator DI = GluedMap.find(OpN); in ScheduleNode()
704 OpN = DI->second; in ScheduleNode()
706 unsigned Degree = OpN->getNodeId(); in ScheduleNode()
708 OpN->setNodeId(--Degree); in ScheduleNode()
[all …]
|
| D | ScheduleDAGSDNodes.cpp | 456 SDNode *OpN = N->getOperand(i).getNode(); in AddSchedEdges() local
457 if (isPassiveNode(OpN)) continue; // Not scheduled. in AddSchedEdges()
458 SUnit *OpSU = &SUnits[OpN->getNodeId()]; in AddSchedEdges()
469 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); in AddSchedEdges()
483 if(isChain && OpN->getOpcode() == ISD::TokenFactor) in AddSchedEdges()
490 computeOperandLatency(OpN, N, i, Dep); in AddSchedEdges()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 181 static bool getUsedBits(unsigned Opc, unsigned OpN, BitVector &Bits,
588 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits() argument
594 if (OpN == D.getNumOperands()-1) in getUsedBits()
606 if (OpN == 1) { in getUsedBits()
619 if (OpN == 1) { in getUsedBits()
627 if (OpN == 1) { in getUsedBits()
637 if (OpN == 1) { in getUsedBits()
692 if (OpN == 1 || OpN == 2) { in getUsedBits()
745 if (OpN == 1) { in getUsedBits()
749 if (OpN == 2) { in getUsedBits()
[all …]
|
| D | HexagonISelLowering.cpp | 2387 SDValue OpN = Op.getOperand(N); in LowerCONCAT_VECTORS() local
2389 if (VT.getSizeInBits() == 64 && OpN.getValueType().getSizeInBits() == 32) { in LowerCONCAT_VECTORS()
2391 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN); in LowerCONCAT_VECTORS()
2397 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or}); in LowerCONCAT_VECTORS()
2399 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or}); in LowerCONCAT_VECTORS()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 3570 SDPatternOperator OpN> {
3573 [(set GPR32:$Rd, (OpN FPR16:$Rn))]> {
3580 [(set GPR64:$Rd, (OpN FPR16:$Rn))]> {
3587 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3593 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3599 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3605 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3611 SDPatternOperator OpN> {
3615 [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn,
3625 [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn,
[all …]
|