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Searched refs:OpNode (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrAVX512.td872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
1068 SDNode OpNode = X86SubVBroadcast> {
1072 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1077 (_Dst.VT (OpNode
1421 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1428 (OpNode (_.VT _.RC:$src1),
1437 (OpNode (_.VT _.RC:$src1),
[all …]
DX86InstrFMA.td145 SDPatternOperator OpNode = null_frag> {
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
195 SDNode OpNode, RegisterClass RC,
199 OpNode>;
225 SDNode OpNode> {
227 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode,
232 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode,
268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
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DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
147 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
149 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
154 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
156 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
161 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
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DX86InstrXOP.td86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
98 (vt128 (OpNode (vt128 VR128:$src1),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
180 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
187 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
195 (vt128 (OpNode (vt128 VR128:$src1),
DX86InstrSSE.td242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
571 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
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DX86InstrCMovSetCC.td83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
87 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
91 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1330 SDNode OpNode>
1332 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1335 SDNode OpNode>
1337 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1343 SDNode OpNode, SDNode OpNode_setflags> {
1344 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1348 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1367 SDPatternOperator OpNode>
1370 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1383 SDPatternOperator OpNode>
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h81 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
83 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
85 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
88 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
90 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
92 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td165 multiclass I3<string OpcStr, SDNode OpNode> {
168 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
172 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
175 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
179 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
182 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
189 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
193 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
197 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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DNVPTXVector.td239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
246 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
250 [(set regclass1:$dst, (OpNode regclass1:$a, regclass2:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
257 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
259 multiclass IntBinVOp<string asmstr, SDNode OpNode,
262 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
264 def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
266 def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
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/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td105 SDPatternOperator OpNode= null_frag> :
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
114 SDPatternOperator OpNode = null_frag> {
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
129 SDPatternOperator OpNode= null_frag> {
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
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DMipsDSPInstrInfo.td260 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
266 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
271 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
277 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
282 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
288 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
298 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
309 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
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DMipsMSAInstrInfo.td1132 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1139 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1143 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1150 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1154 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1161 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1165 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1172 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1176 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1183 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
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DMicroMipsDSPInstrInfo.td160 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
166 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
196 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
202 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
233 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
238 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
265 class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
317 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
322 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
DMipsInstrInfo.td786 SDPatternOperator OpNode = null_frag>:
789 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
799 SDPatternOperator OpNode = null_frag> :
802 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
828 SDPatternOperator OpNode = null_frag,
832 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
837 SDPatternOperator OpNode = null_frag>:
840 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
852 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
855 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
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DMicroMipsInstrInfo.td189 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
193 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
199 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
203 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
289 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
293 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
301 SDPatternOperator OpNode = null_frag> :
304 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
315 SDPatternOperator OpNode = null_frag> :
318 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
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DMipsCondMov.td37 SDPatternOperator OpNode = null_frag> :
40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 SDPatternOperator OpNode = null_frag> :
50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMicroMips32r6InstrInfo.td515 SDPatternOperator OpNode = null_frag,
519 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
542 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
546 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
573 SDPatternOperator OpNode = null_frag>
578 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
603 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
608 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
704 SDPatternOperator OpNode = null_frag>
709 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
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DMips16InstrInfo.td1305 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1306 Mips16Pat<(OpNode CPU16Regs:$r),
1312 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1313 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1325 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1326 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1335 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1336 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1343 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1344 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
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/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td140 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
159 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
178 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
316 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
344 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
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/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2435 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2441 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2500 ValueType TyD, ValueType TyQ, SDNode OpNode>
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2518 ValueType TyQ, ValueType TyD, SDNode OpNode>
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2547 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
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/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
238 SDNode OpNode> {
241 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
244 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
247 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
250 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
259 SDNode OpNode> {
262 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td250 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
274 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
279 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
283 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
288 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
296 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
297 Load<OpcStr, Op3Val, OpNode, RC, Ty> {
298 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
[all …]
DSparcInstrFormats.td212 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
216 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
219 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp3061 TreePatternNode *OpNode = InVal->clone(); in parseInstructionPattern() local
3064 OpNode->clearPredicateFns(); in parseInstructionPattern()
3067 if (Record *Xform = OpNode->getTransformFn()) { in parseInstructionPattern()
3068 OpNode->setTransformFn(nullptr); in parseInstructionPattern()
3070 Children.push_back(OpNode); in parseInstructionPattern()
3071 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes()); in parseInstructionPattern()
3074 ResultNodeOperands.push_back(OpNode); in parseInstructionPattern()
3519 TreePatternNode *OpNode = DstPattern->getChild(ii); in ParsePatterns() local
3520 if (Record *Xform = OpNode->getTransformFn()) { in ParsePatterns()
3521 OpNode->setTransformFn(nullptr); in ParsePatterns()
[all …]

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