/external/valgrind/auxprogs/ |
D | DotToScc.hs | 90 deScc :: (Ord a) => 104 deDepthFirstSearch :: (Ord a) => 126 deSpanningSearch :: (Ord a) => 163 unMkSet :: (Ord a) => Set a -> [a] 170 utSetEmpty :: (Ord a) => Set a 177 utSetIsEmpty :: (Ord a) => Set a -> Bool 184 utSetSingleton :: (Ord a) => a -> Set a 191 utSetFromList :: (Ord a) => [a] -> Set a 202 utSetToList :: (Ord a) => Set a -> [a] 210 utSetUnion :: (Ord a) => Set a -> Set a -> Set a [all …]
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/external/protobuf/python/google/protobuf/ |
D | text_encoding.py | 78 Ord = ord if isinstance(text, basestring) else lambda x: x 80 return ''.join(_cescape_utf8_to_str[Ord(c)] for c in text) 81 return ''.join(_cescape_byte_to_str[Ord(c)] for c in text)
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/external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime.Tests/ |
D | Antlr.Runtime.Tests.pas | 117 CheckEquals(Ord('e'), Stream.LA(1)); 121 CheckEquals(Ord('O'), Stream.LA(1)); 127 CheckEquals(Ord('n'), Stream.LA(1)); 133 CheckEquals(Ord('e'), Stream.LA(1));
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/external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime/ |
D | Antlr.Runtime.Tree.pas | 3893 if ((FC >= Ord('a')) and (FC <= Ord('z'))) 3894 or ((FC >= Ord('A')) and (FC <= Ord('Z'))) 3895 or (FC = Ord('_')) 3899 while ((FC >= Ord('a')) and (FC <= Ord('z'))) 3900 or ((FC >= Ord('A')) and (FC <= Ord('Z'))) 3901 or ((FC >= Ord('0')) and (FC <= Ord('9'))) 3902 or (FC = Ord('_')) do 3910 if (FC = Ord('(')) then 3916 if (FC = Ord(')')) then 3922 if (FC = Ord('%')) then [all …]
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D | Antlr.Runtime.pas | 2436 TOKEN_dot_EOF = Ord(cscEOF);
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 436 AtomicOrdering Ord) const override; 438 Value *Addr, AtomicOrdering Ord) const override; 442 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 444 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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D | ARMISelLowering.cpp | 2878 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); in LowerATOMIC_FENCE() local 2883 } else if (Subtarget->isSwift() && Ord == Release) { in LowerATOMIC_FENCE() 11869 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument 11874 switch (Ord) { in emitLeadingFence() 11897 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument 11902 switch (Ord) { in emitTrailingFence() 11998 AtomicOrdering Ord) const { in emitLoadLinked() 12001 bool IsAcquire = isAtLeastAcquire(Ord); in emitLoadLinked() 12043 AtomicOrdering Ord) const { in emitStoreConditional() 12045 bool IsRelease = isAtLeastRelease(Ord); in emitStoreConditional()
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/external/icu/icu4c/source/data/lang/ |
D | mg.txt | 51 ur{"Ordò"}
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D | ga.txt | 12 collation{"Ord Sórtála"} 416 ducet{"Ord Réamhshocraithe Sórtála Unicode"} 418 standard{"Ord Caighdeánach Sórtála"}
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.h | 235 AtomicOrdering Ord) const override; 237 Value *Addr, AtomicOrdering Ord) const override;
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D | HexagonGenInsert.cpp | 363 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} in OrderedRegisterList() 385 const RegisterOrdering &Ord; member in __anon53296d7a0711::OrderedRegisterList 413 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); in insert() 422 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); in remove()
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D | HexagonISelLowering.cpp | 2853 AtomicOrdering Ord) const { in emitLoadLinked() 2868 Value *Val, Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional()
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/external/llvm/include/llvm/Target/ |
D | TargetLowering.h | 1049 AtomicOrdering Ord) const { in emitLoadLinked() argument 1056 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional() argument 1091 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument 1096 if (isAtLeastRelease(Ord) && IsStore) in emitLeadingFence() 1097 return Builder.CreateFence(Ord); in emitLeadingFence() 1103 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument 1108 if (isAtLeastAcquire(Ord)) in emitTrailingFence() 1109 return Builder.CreateFence(Ord); in emitTrailingFence()
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/external/llvm/test/tools/llvm-objdump/ |
D | coff-private-headers.test | 7 IMPORT-NEXT: Hint/Ord Name
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.h | 343 AtomicOrdering Ord) const override; 345 Value *Addr, AtomicOrdering Ord) const override;
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D | AArch64A57FPLoadBalancing.cpp | 529 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local 530 for (auto Reg : Ord) { in scavengeRegister()
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D | AArch64ISelLowering.cpp | 9924 AtomicOrdering Ord) const { in emitLoadLinked() 9927 bool IsAcquire = isAtLeastAcquire(Ord); in emitLoadLinked() 9967 AtomicOrdering Ord) const { in emitStoreConditional() 9969 bool IsRelease = isAtLeastRelease(Ord); in emitStoreConditional()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.h | 511 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 513 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
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D | PPCISelLowering.cpp | 8100 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument 8102 if (Ord == SequentiallyConsistent) in emitLeadingFence() 8104 if (isAtLeastRelease(Ord)) in emitLeadingFence() 8110 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument 8112 if (IsLoad && isAtLeastAcquire(Ord)) in emitTrailingFence()
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/external/llvm/include/llvm/IR/ |
D | Instructions.h | 57 inline bool isAtLeastAcquire(AtomicOrdering Ord) { in isAtLeastAcquire() argument 58 return (Ord == Acquire || in isAtLeastAcquire() 59 Ord == AcquireRelease || in isAtLeastAcquire() 60 Ord == SequentiallyConsistent); in isAtLeastAcquire() 65 inline bool isAtLeastRelease(AtomicOrdering Ord) { in isAtLeastRelease() argument 66 return (Ord == Release || in isAtLeastRelease() 67 Ord == AcquireRelease || in isAtLeastRelease() 68 Ord == SequentiallyConsistent); in isAtLeastRelease()
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/external/llvm/bindings/ocaml/llvm/ |
D | llvm_ocaml.c | 2000 LLVMValueRef Val, value Ord, in llvm_build_atomicrmw_native() argument 2004 Ptr, Val, Int_val(Ord), Bool_val(ST)); in llvm_build_atomicrmw_native()
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D | llvm.ml | 137 | Ord Constructor
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D | llvm.mli | 194 | Ord (** Ordered (no operand is NaN) *) Constructor
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