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Searched refs:OutR (Results 1 – 2 of 2) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp398 Register OutR(Op0); in convertToPredForm() local
417 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
421 MRI->replaceRegWith(OutR.R, NewOutR); in convertToPredForm()
DHexagonBitSimplify.cpp2335 bool isShuffleOf(unsigned OutR, unsigned InpR) const;
2433 bool HexagonLoopRescheduling::isShuffleOf(unsigned OutR, unsigned InpR) const { in isShuffleOf() argument
2434 if (!BTP->has(OutR) || !BTP->has(InpR)) in isShuffleOf()
2436 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()