Searched refs:PrevReg (Results 1 – 5 of 5) sorted by relevance
212 if (unsigned PrevReg = Result.getRegisterForVar(Var)) in calculateDbgValueHistory() local213 dropRegDescribedVar(RegVars, PrevReg, Var); in calculateDbgValueHistory()
466 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local479 PrevReg = MCRegOp; in expandSET()502 TmpInst.addOperand(PrevReg); in expandSET()
1057 int PrevReg = *RegList.List->begin(); in isRegList16() local1060 if ( Reg != PrevReg + 1) in isRegList16()1062 PrevReg = Reg; in isRegList16()4486 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local4505 unsigned TmpReg = PrevReg + 1; in parseRegisterList()4514 PrevReg = TmpReg; in parseRegisterList()4521 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()4534 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()4558 PrevReg = RegNo; in parseRegisterList()
660 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign() argument664 if (PhysReg == PrevReg) in canReassign()680 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) in canReassign()
3017 int64_t PrevReg = FirstReg; in parseVectorList() local3032 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg); in parseVectorList()3055 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) in parseVectorList()3058 PrevReg = Reg; in parseVectorList()