| /external/llvm/test/Transforms/BBVectorize/ |
| D | req-depth.ll | 3 …torize-req-chain-depth 2 -bb-vectorize-ignore-target-info -S | FileCheck %s -check-prefix=CHECK-RD2
13 ; CHECK-RD2-LABEL: @test1(
15 ; CHECK-RD2: <2 x double>
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| /external/llvm/test/CodeGen/Mips/msa/ |
| D | elm_copy.ll | 101 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
106 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
199 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
204 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
|
| /external/valgrind/none/tests/arm/ |
| D | vfp.c | 113 #define TESTINSN_vmov_2core_2single(instruction, RD1, RD2, SN, SM, SNval, SMval) \ argument
122 "mov " #RD2 ", #0x4\n\t" \
125 "str " #RD2 ", [%0, #+4]\n\t" \
128 : #RD1, #RD2, #SN, #SM, "memory" \
130 printf("%s :: "#RD1" 0x%08x "#RD2" 0x%08x\n", \
173 #define TESTINSN_vmov_2core_double(instruction, RD1, RD2, DN, DNval0, DNval1) \ argument
180 "mov " #RD2 ", #55\n\t" \
184 "str " #RD2 ", [%0, #+4]\n\t" \
187 : #DN, #RD1, #RD2, "memory" \
189 printf("%s :: "#RD1" 0x%08x "#RD2" 0x%08x\n", \
|
| D | v6intARM.c | 100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
111 "mov " #RD2 ",%4;" \
116 "mov %1," #RD2 ";" \
120 : #RD, #RD2, #RM, #RS, "cc", "memory" \
|
| D | v6intThumb.c | 190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ argument
199 "mov " #RD2 ",%4;" \
204 "mov %1," #RD2 ";" \
208 : #RD, #RD2, #RM, #RS, "cc", "memory" \
298 #define TESTINSTPCMISALIGNED_2OUT(instruction, RD, RD2, label, cvin) \ argument
307 "mov " #RD2 ", #0;" \
322 "mov %1, " #RD2 ";" \
326 : #RD, #RD2, "cc", "memory" \
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| D | v6media.c | 109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
118 "mov " #RD2 ",%4;" \
123 "mov %1," #RD2 ";" \
127 : #RD, #RD2, #RM, #RS, "cc", "memory" \
|
| /external/clang/lib/Sema/ |
| D | SemaChecking.cpp | 9539 RecordDecl *RD2) { in isLayoutCompatibleStruct() argument
9544 const CXXRecordDecl *D2CXX = cast<CXXRecordDecl>(RD2); in isLayoutCompatibleStruct()
9559 } else if (const CXXRecordDecl *D2CXX = dyn_cast<CXXRecordDecl>(RD2)) { in isLayoutCompatibleStruct()
9566 RecordDecl::field_iterator Field2 = RD2->field_begin(), in isLayoutCompatibleStruct()
9567 Field2End = RD2->field_end(), in isLayoutCompatibleStruct()
9584 RecordDecl *RD2) { in isLayoutCompatibleUnion() argument
9586 for (auto *Field2 : RD2->fields()) in isLayoutCompatibleUnion()
9609 bool isLayoutCompatible(ASTContext &C, RecordDecl *RD1, RecordDecl *RD2) { in isLayoutCompatible() argument
9610 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
9614 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3027 unsigned RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3028 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3034 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); in emitMSACBranchPseudo()
|