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Searched refs:REX (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp990 unsigned REX = 0; in DetermineREXPrefix() local
994 REX |= 1 << 3; // set REX.W in DetermineREXPrefix()
996 if (MI.getNumOperands() == 0) return REX; in DetermineREXPrefix()
1014 REX |= 0x40; // REX fixed encoding prefix in DetermineREXPrefix()
1022 REX |= 1 << 2; // set REX.R in DetermineREXPrefix()
1027 REX |= 1 << 0; // set REX.B in DetermineREXPrefix()
1033 REX |= 1 << 2; // set REX.R in DetermineREXPrefix()
1040 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) in DetermineREXPrefix()
1056 REX |= 1 << 2; // set REX.R in DetermineREXPrefix()
1062 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) in DetermineREXPrefix()
[all …]
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td54 // with a REX prefix.
60 // X86-64 only, requires REX.
91 // X86-64 only, requires REX.
115 // X86-64 only, requires REX
138 // These also require REX.
325 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
326 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
380 // GR8_NOREX - GR8 registers which do not require a REX prefix.
388 // GR16_NOREX - GR16 registers which do not require a REX prefix.
391 // GR32_NOREX - GR32 registers which do not require a REX prefix.
[all …]
DREADME-X86-64.txt45 requiring REX prefix. However, divb and mulb both produce results in AH. If isel
DX86InstrExtension.td119 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
DX86InstrCompiler.td1327 // This can also reduce instruction size by eliminating the need for the REX
1500 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
DX86InstrFormats.td259 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
DX86InstrArithmetic.td611 /// the 0x40 REX prefix. This is set for i64 types.
DX86InstrInfo.td345 // of a plain GPR, so that it doesn't potentially require a REX prefix.
1489 // encoded when a REX prefix is present.
/external/llvm/test/MC/Disassembler/X86/
Dprefixes.txt64 # Test that MMX ignore REX.R and REX.B.
Dx86-64.txt424 # Try all combinations of EVEX.x and REX.b:
/external/llvm/test/CodeGen/X86/
Dtail-call-win64.ll11 ; Check that we merge the REX prefixes into 0x49 instead of 0x48, 0x41.
Dnorex-subreg.ll11 ; REX prefix, so the destination register must be GR8_NOREX. The code above
/external/valgrind/docs/internals/
D3_7_BUGSTATUS.txt48 == 278744 REX.W CVTPS2PD
49 **possible 3.8.0 (redundant REX prefix)
D3_8_BUGSTATUS.txt140 redundant-REX, should be easy to fix
D3_2_BUGSTATUS.txt182 vx1740 vx1754 32 n-i-bz handle REX.W fsqrt
/external/pcre/dist/sljit/
DsljitNativeX86_common.c114 #define REX 0x40 macro
2697 *inst++ = (reg_map[TMP_REG1] <= 7) ? REX : REX_B;
2701 *inst++ = REX | (reg_map[TMP_REG1] <= 7 ? 0 : REX_R) | (reg_map[dst] <= 7 ? 0 : REX_B);
2713 *inst++ = (reg_map[reg] <= 7) ? REX : REX_B;
DsljitNativeX86_64.c378 rex |= REX; in emit_x86_instruction()
/external/valgrind/
DNEWS1867 279071 JDK creates PTEST with redundant REX.W prefix
1932 210481 vex amd64->IR: Assertion `sz == 2 || sz == 4' failed (REX.W POPQ)
/external/llvm/docs/
DLangRef.rst3471 existed since i386, and can be accessed without the REX prefix.
/external/icu/icu4c/source/data/unidata/
DUnicodeData.txt12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;
Dppucd.txt15843 cp;A3D1;na=YI SYLLABLE REX
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DUnicodeData.txt12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DUnicodeData.txt12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;