Searched refs:REX (Results 1 – 23 of 23) sorted by relevance
/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCCodeEmitter.cpp | 990 unsigned REX = 0; in DetermineREXPrefix() local 994 REX |= 1 << 3; // set REX.W in DetermineREXPrefix() 996 if (MI.getNumOperands() == 0) return REX; in DetermineREXPrefix() 1014 REX |= 0x40; // REX fixed encoding prefix in DetermineREXPrefix() 1022 REX |= 1 << 2; // set REX.R in DetermineREXPrefix() 1027 REX |= 1 << 0; // set REX.B in DetermineREXPrefix() 1033 REX |= 1 << 2; // set REX.R in DetermineREXPrefix() 1040 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) in DetermineREXPrefix() 1056 REX |= 1 << 2; // set REX.R in DetermineREXPrefix() 1062 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) in DetermineREXPrefix() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 54 // with a REX prefix. 60 // X86-64 only, requires REX. 91 // X86-64 only, requires REX. 115 // X86-64 only, requires REX 138 // These also require REX. 325 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 326 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 380 // GR8_NOREX - GR8 registers which do not require a REX prefix. 388 // GR16_NOREX - GR16 registers which do not require a REX prefix. 391 // GR32_NOREX - GR32 registers which do not require a REX prefix. [all …]
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D | README-X86-64.txt | 45 requiring REX prefix. However, divb and mulb both produce results in AH. If isel
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D | X86InstrExtension.td | 119 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
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D | X86InstrCompiler.td | 1327 // This can also reduce instruction size by eliminating the need for the REX 1500 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
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D | X86InstrFormats.td | 259 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
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D | X86InstrArithmetic.td | 611 /// the 0x40 REX prefix. This is set for i64 types.
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D | X86InstrInfo.td | 345 // of a plain GPR, so that it doesn't potentially require a REX prefix. 1489 // encoded when a REX prefix is present.
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/external/llvm/test/MC/Disassembler/X86/ |
D | prefixes.txt | 64 # Test that MMX ignore REX.R and REX.B.
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D | x86-64.txt | 424 # Try all combinations of EVEX.x and REX.b:
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/external/llvm/test/CodeGen/X86/ |
D | tail-call-win64.ll | 11 ; Check that we merge the REX prefixes into 0x49 instead of 0x48, 0x41.
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D | norex-subreg.ll | 11 ; REX prefix, so the destination register must be GR8_NOREX. The code above
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/external/valgrind/docs/internals/ |
D | 3_7_BUGSTATUS.txt | 48 == 278744 REX.W CVTPS2PD 49 **possible 3.8.0 (redundant REX prefix)
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D | 3_8_BUGSTATUS.txt | 140 redundant-REX, should be easy to fix
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D | 3_2_BUGSTATUS.txt | 182 vx1740 vx1754 32 n-i-bz handle REX.W fsqrt
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/external/pcre/dist/sljit/ |
D | sljitNativeX86_common.c | 114 #define REX 0x40 macro 2697 *inst++ = (reg_map[TMP_REG1] <= 7) ? REX : REX_B; 2701 *inst++ = REX | (reg_map[TMP_REG1] <= 7 ? 0 : REX_R) | (reg_map[dst] <= 7 ? 0 : REX_B); 2713 *inst++ = (reg_map[reg] <= 7) ? REX : REX_B;
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D | sljitNativeX86_64.c | 378 rex |= REX; in emit_x86_instruction()
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/external/valgrind/ |
D | NEWS | 1867 279071 JDK creates PTEST with redundant REX.W prefix 1932 210481 vex amd64->IR: Assertion `sz == 2 || sz == 4' failed (REX.W POPQ)
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/external/llvm/docs/ |
D | LangRef.rst | 3471 existed since i386, and can be accessed without the REX prefix.
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/external/icu/icu4c/source/data/unidata/ |
D | UnicodeData.txt | 12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;
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D | ppucd.txt | 15843 cp;A3D1;na=YI SYLLABLE REX
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/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
D | UnicodeData.txt | 12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;
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/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/ |
D | UnicodeData.txt | 12943 A3D1;YI SYLLABLE REX;Lo;0;L;;;;;N;;;;;
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