Searched refs:RHS2 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/include/llvm/ADT/ |
| D | SparseBitVector.h | 233 const SparseBitVectorElement &RHS2,
239 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
698 const SparseBitVector<ElementSize> &RHS2)
701 intersectWithComplement(RHS2);
703 } else if (this == &RHS2) {
704 SparseBitVector RHS2Copy(RHS2);
712 ElementListConstIter Iter2 = RHS2.Elements.begin();
720 while (Iter2 != RHS2.Elements.end()) {
756 const SparseBitVector<ElementSize> *RHS2) {
757 intersectWithComplement(*RHS1, *RHS2);
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 1068 Value *LHS, *RHS, *LHS2, *RHS2; in visitSelectInst() local
1103 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor) in visitSelectInst()
1104 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(LHS),SPF2,LHS2,RHS2, in visitSelectInst()
1107 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor) in visitSelectInst()
1108 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(RHS),SPF2,LHS2,RHS2, in visitSelectInst()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3781 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
3783 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
3785 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); in OptimizeVFPBrcond()
3789 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
8020 unsigned RHS2 = MI->getOperand(4).getReg(); in EmitInstrWithCustomInserter() local
8025 .addReg(LHS2).addReg(RHS2) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 14262 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); in Lower256IntVSETCC() local
14269 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); in Lower256IntVSETCC()
17941 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); in Lower256IntArith() local
17948 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); in Lower256IntArith()
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