Searched refs:RS1 (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
138 Inst.addOperand(RS1); in EmitBinary()
144 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR() argument
146 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); in EmitOR()
150 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD() argument
152 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI); in EmitADD()
156 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitSHL() argument
158 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI); in EmitSHL()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 895 unsigned RS1 = getRegState(Op1); in splitAslOr() local
919 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
922 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
926 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR) in splitAslOr()
936 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
948 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
950 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
959 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR); in splitAslOr()
961 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
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