Searched refs:RecVec (Results 1 – 7 of 7) sorted by relevance
30 typedef std::vector<Record*> RecVec; typedef36 void splitSchedReadWrites(const RecVec &RWDefs,37 RecVec &WriteDefs, RecVec &ReadDefs);56 RecVec Aliases;100 RecVec PredTerm;143 RecVec InstRWs;186 RecVec ItinDefList;190 RecVec ItinRWDefs;193 RecVec WriteResDefs;194 RecVec ReadAdvanceDefs;[all …]
133 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); in collectProcModels()173 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, in scanSchedRW()180 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()186 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()189 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()206 RecVec SWDefs, SRDefs; in collectSchedRW()211 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()222 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedRW()225 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()237 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectSchedRW()[all …]
92 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,622 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()763 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()770 RecVec SubResources; in ExpandProcResources()795 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources"); in ExpandProcResources()890 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); in GenSchedClassTables()943 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()987 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
1423 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
677 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
65 typedef std::vector<Record*> RecVec; typedef94 typedef std::map<Record*, RecVec> ExpandMap;136 const RecVec *expand(Record *Set);
26 typedef SetTheory::RecVec RecVec; typedef220 if (const RecVec *Result = ST.expand(Rec)) in apply()275 if (const RecVec *Result = expand(Def->getDef())) in evaluate()298 const RecVec *SetTheory::expand(Record *Set) { in expand()313 RecVec &EltVec = Expansions[Set]; in expand()