| /external/v8/test/unittests/compiler/ |
| D | register-allocator-unittest.cc | 97 auto c_reg = EmitOI(Reg(1), Reg(a_reg, 1), Reg(b_reg, 0)); in TEST_F()
117 auto ipp = EmitOI(Same(), Reg(phi), Use(DefineConstant())); in TEST_F()
132 EndBlock(Branch(Reg(i), 1, 2)); in TEST_F()
150 EndBlock(Branch(Reg(param), 1, 2)); in TEST_F()
169 EndBlock(Branch(Reg(DefineConstant()), 1, 2)); in TEST_F()
180 Return(Reg(Phi(t_val, f_val))); in TEST_F()
191 EndBlock(Branch(Reg(DefineConstant()), 1, 2)); in TEST_F()
228 EndBlock(Branch(Reg(DefineConstant()), 1, 2)); in TEST_F()
238 EndBlock(Branch(Reg(DefineConstant()), 1, 2)); in TEST_F()
251 Return(EmitCall(Reg(0), kPhis, merged)); in TEST_F()
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| D | move-optimizer-unittest.cc | 92 AddMove(first_instr, Reg(0), Reg(1)); in TEST_F()
94 AddMove(last_instr, Reg(1), Reg(0)); in TEST_F()
102 CHECK(Contains(move, Reg(0), Reg(1))); in TEST_F()
116 AddMove(first_instr, Reg(first_reg_index), ExplicitReg(second_reg_index)); in TEST_F()
118 AddMove(last_instr, Reg(second_reg_index), Reg(first_reg_index)); in TEST_F()
126 CHECK(Contains(move, Reg(first_reg_index), ExplicitReg(second_reg_index))); in TEST_F()
137 AddMove(gap, Const(1), Reg(0)); in TEST_F()
144 CHECK(Contains(move, Const(1), Reg(0))); in TEST_F()
148 CHECK(Contains(move, Reg(0), Slot(0))); in TEST_F()
149 CHECK(Contains(move, Reg(0), Slot(1))); in TEST_F()
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 40 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
42 VRegInfo[Reg].first = RC; in setRegClass()
46 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
49 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
58 setRegClass(Reg, NewRC); in constrainRegClass()
63 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass() argument
65 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
74 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
83 setRegClass(Reg, NewRC); in recomputeRegClass()
97 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
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| D | AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
154 unsigned Reg = *AI; in StartBlock() local
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| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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| D | CriticalAntiDepBreaker.cpp | 62 unsigned Reg = *AI; in StartBlock() local
63 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
64 KillIndices[Reg] = BBSize; in StartBlock()
65 DefIndices[Reg] = ~0u; in StartBlock()
77 unsigned Reg = *AI; in StartBlock() local
78 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
79 KillIndices[Reg] = BBSize; in StartBlock()
80 DefIndices[Reg] = ~0u; in StartBlock()
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
104 if (KillIndices[Reg] != ~0u) { in Observe()
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| D | RegisterPressure.cpp | 62 for (unsigned Reg : LiveInRegs) in dump() local
63 dbgs() << PrintVRegOrUnit(Reg, TRI) << " "; in dump()
66 for (unsigned Reg : LiveOutRegs) in dump() local
67 dbgs() << PrintVRegOrUnit(Reg, TRI) << " "; in dump()
174 static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) { in getLiveRange() argument
175 if (TargetRegisterInfo::isVirtualRegister(Reg)) in getLiveRange()
176 return &LIS.getInterval(Reg); in getLiveRange()
177 return LIS.getCachedRegUnit(Reg); in getLiveRange()
301 for (unsigned Reg : P.LiveOutRegs) { in initLiveThru() local
302 if (TargetRegisterInfo::isVirtualRegister(Reg) in initLiveThru()
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| D | MachineInstrBundle.cpp | 145 unsigned Reg = MO.getReg(); in finalizeBundle() local
146 if (!Reg) in finalizeBundle()
148 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
149 if (LocalDefSet.count(Reg)) { in finalizeBundle()
153 KilledDefSet.insert(Reg); in finalizeBundle()
155 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
156 ExternUses.push_back(Reg); in finalizeBundle()
158 UndefUseSet.insert(Reg); in finalizeBundle()
162 KilledUseSet.insert(Reg); in finalizeBundle()
168 unsigned Reg = MO.getReg(); in finalizeBundle() local
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| D | MachineVerifier.cpp | 91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { in addRegWithSubRegs()
92 RV.push_back(Reg); in addRegWithSubRegs()
93 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in addRegWithSubRegs()
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs()
129 bool addPassed(unsigned Reg) { in addPassed()
130 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addPassed()
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) in addPassed()
134 return vregsPassed.insert(Reg).second; in addPassed()
148 bool addRequired(unsigned Reg) { in addRequired()
149 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addRequired()
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| D | RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed() argument
35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) { in setRegUsed()
45 I->Reg = 0; in initRegState()
95 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits() argument
96 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
129 unsigned Reg = MO.getReg(); in determineKillsAndDefs() local
130 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
138 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
142 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
144 addRegUnits(DefRegUnits, Reg); in determineKillsAndDefs()
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| D | LivePhysRegs.cpp | 50 unsigned Reg = O->getReg(); in stepBackward() local
51 if (Reg == 0) in stepBackward()
53 removeReg(Reg); in stepBackward()
62 unsigned Reg = O->getReg(); in stepBackward() local
63 if (Reg == 0) in stepBackward()
65 addReg(Reg); in stepBackward()
78 unsigned Reg = O->getReg(); in stepForward() local
79 if (Reg == 0) in stepForward()
84 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
89 removeReg(Reg); in stepForward()
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| D | PeepholeOptimizer.cpp | 160 bool findNextSource(unsigned Reg, unsigned SubReg,
178 bool isNAPhysCopy(unsigned Reg);
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { in ValueTrackerResult() argument
226 addSource(Reg, SubReg); in ValueTrackerResult()
252 return RegSrcs[Idx].Reg; in getSrcReg()
300 unsigned Reg; member in __anon2734e12b0111::ValueTracker
350 ValueTracker(unsigned Reg, unsigned DefSubReg, in ValueTracker() argument
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
356 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) { in ValueTracker()
357 Def = MRI.getVRegDef(Reg); in ValueTracker()
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| D | RegAllocFast.cpp | 710 unsigned Reg = MO.getReg(); in handleThroughOperands() local
711 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in handleThroughOperands()
714 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
715 if (ThroughRegs.insert(Reg).second) in handleThroughOperands()
716 DEBUG(dbgs() << ' ' << PrintReg(Reg)); in handleThroughOperands()
726 unsigned Reg = MO.getReg(); in handleThroughOperands() local
727 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; in handleThroughOperands()
728 markRegUsedInInstr(Reg); in handleThroughOperands()
729 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in handleThroughOperands()
740 unsigned Reg = MO.getReg(); in handleThroughOperands() local
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| D | StackMaps.cpp | 78 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { in getDwarfRegNum() argument
79 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum()
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
102 unsigned Reg = (++MOI)->getReg(); in parseOperand() local
105 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
111 unsigned Reg = (++MOI)->getReg(); in parseOperand() local
114 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
180 OS << TRI->getName(Loc.Reg); in print()
182 OS << Loc.Reg; in print()
187 OS << TRI->getName(Loc.Reg); in print()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
91 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
95 return MO->Contents.Reg.Next; in getNextOperandForReg()
204 void verifyUseList(unsigned Reg) const;
236 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
237 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
252 reg_instructions(unsigned Reg) const { in reg_instructions() argument
253 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
267 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
268 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
287 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands() argument
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| D | LiveIntervalAnalysis.h | 110 LiveInterval &getInterval(unsigned Reg) { in getInterval() argument
111 if (hasInterval(Reg)) in getInterval()
112 return *VirtRegIntervals[Reg]; in getInterval()
114 return createAndComputeVirtRegInterval(Reg); in getInterval()
117 const LiveInterval &getInterval(unsigned Reg) const { in getInterval() argument
118 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
121 bool hasInterval(unsigned Reg) const { in hasInterval() argument
122 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; in hasInterval()
126 LiveInterval &createEmptyInterval(unsigned Reg) { in createEmptyInterval() argument
127 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
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| D | LiveVariables.h | 110 unsigned Reg,
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
188 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
195 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
285 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { in isLiveIn() argument
286 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 113 RegOp Reg; member
148 Op->Reg.Kind = Kind; in createReg()
149 Op->Reg.Num = Num; in createReg()
200 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
204 return Reg.Num; in getReg()
365 bool parseRegister(Register &Reg);
367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
495 bool SystemZAsmParser::parseRegister(Register &Reg) { in parseRegister() argument
496 Reg.StartLoc = Parser.getTok().getLoc(); in parseRegister()
505 return Error(Reg.StartLoc, "invalid register"); in parseRegister()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | DynamicTypeMap.cpp | 22 const MemRegion *Reg) { in getDynamicTypeInfo() argument
23 Reg = Reg->StripCasts(); in getDynamicTypeInfo()
26 const DynamicTypeInfo *GDMType = State->get<DynamicTypeMap>(Reg); in getDynamicTypeInfo()
31 if (const TypedRegion *TR = dyn_cast<TypedRegion>(Reg)) in getDynamicTypeInfo()
34 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) { in getDynamicTypeInfo()
42 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, in setDynamicTypeInfo() argument
44 Reg = Reg->StripCasts(); in setDynamicTypeInfo()
45 ProgramStateRef NewState = State->set<DynamicTypeMap>(Reg, NewTy); in setDynamicTypeInfo()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 67 bool contains(unsigned Reg) const { in contains() argument
68 unsigned InByte = Reg % 8; in contains()
69 unsigned Byte = Reg / 8; in contains()
338 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
342 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
456 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
473 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) in MCSubRegIndexIterator() argument
474 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator()
475 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; in MCSubRegIndexIterator()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 95 bool contains(unsigned Reg) const { in contains() argument
96 return MC->contains(Reg); in contains()
282 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
283 return int(Reg) >= (1 << 30); in isStackSlot()
287 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
288 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
289 return int(Reg - (1u << 30)); in stackSlot2Index()
300 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
301 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
302 return int(Reg) > 0; in isPhysicalRegister()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 56 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset; in SystemZFrameLowering()
100 unsigned Reg = CSRegs[I]; in determineCalleeSaves() local
101 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) { in determineCalleeSaves()
144 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
145 if (SystemZ::GR64BitRegClass.contains(Reg)) { in spillCalleeSavedRegisters()
146 unsigned Offset = RegSpillOffsets[Reg]; in spillCalleeSavedRegisters()
149 LowGPR = Reg; in spillCalleeSavedRegisters()
165 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; in spillCalleeSavedRegisters() local
166 unsigned Offset = RegSpillOffsets[Reg]; in spillCalleeSavedRegisters()
168 LowGPR = Reg; StartOffset = Offset; in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 43 bool operator== (const Register &Reg) const { in operator ==()
44 return R == Reg.R && S == Reg.S; in operator ==()
46 bool operator< (const Register &Reg) const { in operator <()
47 return R < Reg.R || (R == Reg.R && S < Reg.S); in operator <()
51 PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {} in PrintRegister()
54 Register Reg; member
60 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
93 void processPredicateGPR(const Register &Reg);
98 Register getPredRegFor(const Register &Reg);
206 void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { in processPredicateGPR() argument
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1012 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass() local
1013 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR64RegisterClass()
1023 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass() local
1024 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16RegisterClass()
1034 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass() local
1035 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16ZeroRegisterClass()
1045 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass() local
1046 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRMM16MovePRegisterClass()
1056 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass() local
1057 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
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