| /external/llvm/lib/CodeGen/ |
| D | SplitKit.cpp | 362 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
368 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
375 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), in defValue()
398 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { in forceRecompute() argument
400 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; in forceRecompute()
413 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in forceRecompute()
419 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, in defFromParent() argument
426 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
430 bool Late = RegIdx != 0; in defFromParent()
447 return defValue(RegIdx, ParentVNI, Def); in defFromParent()
[all …]
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| D | SplitKit.h | 298 LiveRangeCalc &getLRCalc(unsigned RegIdx) { in getLRCalc() argument
299 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; in getLRCalc()
307 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
313 void forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI);
317 VNInfo *defFromParent(unsigned RegIdx,
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| D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { in getVarInfo() argument
86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && in getVarInfo()
88 VirtRegInfo.grow(RegIdx); in getVarInfo()
89 return VirtRegInfo[RegIdx]; in getVarInfo()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 633 struct RegIdxOp RegIdx; member
647 Op->RegIdx.Index = Index; in CreateReg()
648 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
649 Op->RegIdx.Kind = RegKind; in CreateReg()
659 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
660 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
662 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
668 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
670 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPRMM16Reg()
676 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR64Reg()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
251 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
253 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
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| D | ARMISelLowering.cpp | 3116 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local
3117 if (RegIdx != array_lengthof(GPRArgRegs)) in LowerFormalArguments()
3118 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); in LowerFormalArguments()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset; in computeIndirectRegAndOffset() local
416 if (RegIdx < 0) { in computeIndirectRegAndOffset()
417 Offset = RegIdx; in computeIndirectRegAndOffset()
418 RegIdx = 0; in computeIndirectRegAndOffset()
423 Reg = RC->getRegister(RegIdx); in computeIndirectRegAndOffset()
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 213 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); in printRegOperand() local
215 O << Type << RegIdx; in printRegOperand()
219 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; in printRegOperand()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) { in getMSACtrlReg()
806 SDValue RegIdx = Node->getOperand(2); in selectNode() local
808 getMSACtrlReg(RegIdx), MVT::i32); in selectNode()
838 SDValue RegIdx = Node->getOperand(2); in selectNode() local
841 getMSACtrlReg(RegIdx), Value); in selectNode()
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| D | MipsSEISelDAGToDAG.h | 33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveVariables.h | 274 VarInfo &getVarInfo(unsigned RegIdx);
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2305 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local
2306 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx); in fastLowerIntrinsicCall()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5606 unsigned RegIdx = 3; in shouldOmitPredicateOperand() local
5613 RegIdx = 4; in shouldOmitPredicateOperand()
5615 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
5617 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
5619 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
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