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Searched refs:RegIndex (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.cpp121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
123 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
137 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
144 calculateIndirectAddress(RegIndex, Channel), in expandPostRAPseudo()
286 unsigned RegIndex; in getIndirectIndexBegin() local
288 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; in getIndirectIndexBegin()
289 ++RegIndex) { in getIndirectIndexBegin()
290 if (IndirectRC->getRegister(RegIndex) == Reg) in getIndirectIndexBegin()
293 Offset = std::max(Offset, (int)RegIndex); in getIndirectIndexBegin()
DAMDGPUInstrInfo.h164 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
DR600InstrInfo.h217 unsigned calculateIndirectAddress(unsigned RegIndex,
DSIInstrInfo.h422 unsigned calculateIndirectAddress(unsigned RegIndex,
DR600ISelLowering.cpp619 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerOperation() local
620 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
653 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerOperation() local
654 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
DR600InstrInfo.cpp1094 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress() argument
1098 return RegIndex; in calculateIndirectAddress()
DSIInstrInfo.cpp2613 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress() argument
2616 return RegIndex; in calculateIndirectAddress()
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp99 int64_t RegIndex = MI->getOperand(1).getImm(); in EmitInstrWithCustomInserter() local
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex); in EmitInstrWithCustomInserter()
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerOperation() local
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerOperation() local
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
/external/llvm/lib/CodeGen/
DRegisterCoalescer.cpp1114 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
1117 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1126 VNInfo *SVNI = SR.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1127 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex)); in eliminateUndefCopy()
1132 LIS->removeVRegDefAt(DstLI, RegIndex); in eliminateUndefCopy()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp547 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
3676 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT() argument
3677 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) in warnIfRegIndexIsAT()
3678 Warning(Loc, "used $at (currently $" + Twine(RegIndex) + in warnIfRegIndexIsAT()