| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 57 RegPressure.resize(NumRC); in ResourcePriorityQueue()
59 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
377 if ((RegPressure[RC->getID()] + in regPressureDelta()
379 (RegPressure[RC->getID()] + in regPressureDelta()
491 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
502 if (RegPressure[RC->getID()] > in scheduledNode()
504 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
505 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| D | ScheduleDAGRRList.cpp | 1651 std::vector<unsigned> RegPressure; member in __anon884f54d00211::RegReductionPQBase
1671 RegPressure.resize(NumRC); in RegReductionPQBase()
1673 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1697 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
1947 unsigned RP = RegPressure[Id]; in dumpRegPressure()
1974 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1993 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2025 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2040 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2087 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 310 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /external/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 101 SmallVector<unsigned, 8> RegPressure; member in __anon19b931500111::MachineLICM
149 RegPressure.clear(); in releaseMemory()
286 RegPressure.resize(NumRPS); in runOnMachineFunction()
287 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
596 BackTrace.push_back(RegPressure); in EnterScope()
768 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
791 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
792 RegPressure[Class] = 0; in UpdateRegPressure()
794 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 53 std::vector<unsigned> RegPressure; variable
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| D | MachineScheduler.h | 374 IntervalPressure RegPressure; variable
395 ShouldTrackPressure(false), RPTracker(RegPressure), in ScheduleDAGMILive()
415 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 104 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 226 setSchedulingPreference(Sched::RegPressure); in InitAMDILLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 70 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1025 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1280 return Sched::RegPressure; in getSchedulingPreference()
1291 return Sched::RegPressure; in getSchedulingPreference()
1299 return Sched::RegPressure; in getSchedulingPreference()
1304 return Sched::RegPressure; in getSchedulingPreference()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 288 setSchedulingPreference(Sched::RegPressure); in SITargetLowering()
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| D | AMDGPUISelLowering.cpp | 384 setSchedulingPreference(Sched::RegPressure); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 133 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 123 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 93 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()
|