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Searched refs:RegType (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV5.td907 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
915 let Inst{27-24} = RegType;
DHexagonInstrInfo.td1259 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1273 let Inst{27-24} = RegType;
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp4694 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType)); in optimizeSwitchInst() local
4695 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst()
/external/llvm/include/llvm/Target/
DTarget.td156 // RegType - Specify the list ValueType of the registers in this register