Searched refs:RegWidth (Results 1 – 5 of 5) sorted by relevance
861 template<int RegWidth, int Shift>869 if (RegWidth == 32) in isMOVZMovAlias()879 template<int RegWidth, int Shift>893 if (RegWidth == 32) in isMOVNMovAlias()3828 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local3831 RegWidth = 64; in MatchAndEmitInstruction()3833 RegWidth = 32; in MatchAndEmitInstruction()3835 if (LSB >= RegWidth) in MatchAndEmitInstruction()3838 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()3843 if (RegWidth == 32) in MatchAndEmitInstruction()[all …]
479 static int getRegClass(bool IsVgpr, unsigned RegWidth) { in getRegClass() argument481 switch (RegWidth) { in getRegClass()492 switch (RegWidth) { in getRegClass()538 unsigned RegWidth; in ParseRegister() local542 RegWidth = 1; in ParseRegister()569 RegWidth = (RegHi - RegLo) + 1; in ParseRegister()575 unsigned Size = std::min(RegWidth, 4u); in ParseRegister()583 int RCID = getRegClass(IsVgpr, RegWidth); in ParseRegister()
803 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local804 return (BitWidth + RegWidth - 1) / RegWidth; in getNumRegisters()
4695 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local4697 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchInst()4706 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchInst()4723 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth); in optimizeSwitchInst()
195 template<unsigned RegWidth>197 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()2140 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument2176 if (FBits == 0 || FBits > RegWidth) return false; in SelectCVTFixedPosOperand()