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Searched refs:ResultVT (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/IR/
DValueTypes.cpp42 EVT ResultVT; in getExtendedVectorVT() local
43 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements); in getExtendedVectorVT()
44 assert(ResultVT.isExtended() && "Type is not extended!"); in getExtendedVectorVT()
45 return ResultVT; in getExtendedVectorVT()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp223 EVT ResultVT = N->getValueType(i); in run() local
224 switch (getTypeAction(ResultVT)) { in run()
245 assert(isLegalInHWReg(ResultVT) && in run()
DDAGCombiner.cpp12079 EVT ResultVT = EVE->getValueType(0); in ReplaceExtractVectorEltOfLoadWithNarrowedLoad() local
12117 if (ResultVT.bitsGT(VecEltVT)) { in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
12120 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
12125 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI, in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
12135 if (ResultVT.bitsLT(VecEltVT)) in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
12136 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load); in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
12138 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load); in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp4440 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, in ExtractSubVector() local
4445 return DAG.getUNDEF(ResultVT); in ExtractSubVector()
4457 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in ExtractSubVector()
4461 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in ExtractSubVector()
4494 EVT ResultVT = Result.getValueType(); in InsertSubVector() local
4505 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in InsertSubVector()
4525 EVT ResultVT = Result.getValueType(); in Insert128BitVector() local
4527 SDValue Undef = DAG.getUNDEF(ResultVT); in Insert128BitVector()
4528 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef, in Insert128BitVector()
4532 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT(); in Insert128BitVector()
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/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp185 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,