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Searched refs:Rounding (Results 1 – 19 of 19) sorted by relevance

/external/llvm/include/llvm/IR/
DIntrinsicsAArch64.td176 // Vector Rounding Halving Add
191 // Vector Rounding Add High-Half
197 // Vector Saturating Rounding Doubling Multiply High
236 // Vector Rounding Subtract High-Half
312 // Vector Rounding Shift Left
316 // Vector Saturating Rounding Shift Left
326 // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
333 // Vector Rounding Narrowing Shift Right by Constant
336 // Vector Rounding Narrowing Saturating Shift Right by Constant
412 // Vector FP Rounding: only ties to even is unrepresented by a normal
DIntrinsicsARM.td315 // Vector Rounding Shift.
328 // Vector Saturating Rounding Shift.
397 // Vector Rounding
/external/libweave/third_party/chromium/base/third_party/dmg_fp/
Ddtoa.cc389 #define Rounding Flt_Rounds macro
3600 int Rounding; variable
3602 Rounding = Flt_Rounds;
3604 Rounding = 1;
3606 case FE_TOWARDZERO: Rounding = 0; break;
3607 case FE_UPWARD: Rounding = 2; break;
3608 case FE_DOWNWARD: Rounding = 3;
3658 if (Rounding >= 2) {
3660 Rounding = Rounding == 2 ? 0 : 2;
3662 if (Rounding != 2)
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt480 # Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
1481 # Scalar Integer Saturating Rounding Doubling Multiply Half High
1826 # Scalar Signed Rounding Shift Right (Immediate)
1832 # Scalar Unigned Rounding Shift Right (Immediate)
1850 # Scalar Signed Rounding Shift Right and Accumulate (Immediate)
1856 # Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
2532 # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To
2539 # Scalar Floating-point Convert To Signed Integer, Rounding To Nearest
2549 # Scalar Floating-point Convert To Unsigned Integer, Rounding To
2558 # Scalar Floating-point Convert To Signed Integer, Rounding Toward
[all …]
/external/clang/include/clang/Basic/
Darm_neon.td1357 // Scalar Saturating Rounding Shift Left
1367 // Signed/Unsigned Rounding Shift Right (Immediate)
1372 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
1431 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1436 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1440 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
1641 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1646 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1650 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
/external/opencv3/3rdparty/openexr/
DChangeLog.ilmbase88 * Rounding during float-to-half conversion now implements
/external/vulkan-validation-layers/libs/glm/detail/
Dtype_half.inl189 // Rounding may cause the significand to overflow and make
/external/valgrind/none/tests/mips32/
Dround.stdout.exp1 -------------------------- test FPU Conversion Operations Using a Directed Rounding Mode ----------…
386 -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode ------------…
Dround_fpu64.stdout.exp1 -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode ------------…
/external/vixl/doc/
Dsupported-instructions.md2858 Rounding add narrow returning high half.
2867 Rounding add narrow returning high half (second part).
2908 Rounding shift right narrow by immediate.
2917 Rounding shift right narrow by immediate (second part).
2926 Rounding subtract narrow returning high half.
2935 Rounding subtract narrow returning high half (second part).
/external/libvpx/libvpx/vp8/common/x86/
Didctllm_sse2.asm395 ; Rounding to dequant and downshift
/external/valgrind/none/tests/mips64/
Dround.stdout.exp1 -------------------------- test FPU Conversion Operations Using a Directed Rounding Mode ----------…
722 -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode ------------…
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4143 // VRHADD : Vector Rounding Halving Add
4159 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4251 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4363 // v8.1a Neon Rounding Double Multiply-Op vector operations,
4364 // VQRDMLAH : Vector Saturating Rounding Doubling Multiply Accumulate Long
4434 // VQRDMLSH : Vector Saturating Rounding Doubling Multiply Subtract Long
4698 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
5477 // VRSHL : Vector Rounding Shift
5484 // VRSHR : Vector Rounding Shift Right
5490 // VRSHRN : Vector Rounding Shift Right and Narrow
[all …]
DARMInstrThumb2.td2614 // Rounding variants of the below included for disassembly only
2625 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2635 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2646 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2656 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2667 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2677 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
/external/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td822 // Rounding mode should agree with SystemZInstrFP.td.
828 // Rounding mode should agree with SystemZInstrFP.td.
/external/icu/icu4c/source/test/testdata/
Ddcfmtest.txt69 # Rounding Modes
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td626 // Rounding Instructions
/external/valgrind/
DNEWS1127 312571 Rounding mode call wrong for the DFP Iops [..]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td9063 // AdvSIMD v8.1 Rounding Double Multiply Add/Subtract