Home
last modified time | relevance | path

Searched refs:SINT_TO_FP (Results 1 – 25 of 33) sorted by relevance

12

/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp103 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
106 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
112 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
118 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
122 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
DARMISelLowering.cpp104 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
109 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
675 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3946 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
3948 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
3966 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
6436 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
6437 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
6469 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
223 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
225 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost()
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
[all …]
DAArch64ISelLowering.cpp179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
481 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
558 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
567 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); in AArch64TargetLowering()
569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); in AArch64TargetLowering()
572 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); in AArch64TargetLowering()
574 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); in AArch64TargetLowering()
577 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
574 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
575 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
578 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, in getCastInstrCost()
579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
580 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
667 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, in getCastInstrCost()
668 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, in getCastInstrCost()
[all …]
DX86IntrinsicsInfo.h507 ISD::SINT_TO_FP, 0),
509 ISD::SINT_TO_FP, 0), // no rm
511 ISD::SINT_TO_FP, 0),
513 ISD::SINT_TO_FP, 0),
515 ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er
577 ISD::SINT_TO_FP, 0),
579 ISD::SINT_TO_FP, 0),
581 ISD::SINT_TO_FP, ISD::SINT_TO_FP),
583 ISD::SINT_TO_FP, 0),
585 ISD::SINT_TO_FP, 0),
[all …]
DREADME-FPStack.txt49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
DX86ISelLowering.cpp184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); in X86TargetLowering()
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); in X86TargetLowering()
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
745 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
[all …]
DX86InstrFragmentsSIMD.td539 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
541 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
/external/llvm/test/CodeGen/X86/
Dpr23273.ll5 ; for SINT_TO_FP wrongly assumed that the target had at least SSE2.
/external/llvm/test/CodeGen/AMDGPU/
Ddagcombiner-bug-illegal-vec4-int-to-fp.ll7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp339 case ISD::SINT_TO_FP: in LegalizeOp()
387 case ISD::SINT_TO_FP: in Promote()
978 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
1005 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
1007 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
DLegalizeFloatTypes.cpp109 case ISD::SINT_TO_FP: in SoftenFloatResult()
690 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
1026 case ISD::SINT_TO_FP: in ExpandFloatResult()
1393 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1405 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
1890 case ISD::SINT_TO_FP: in PromoteFloatResult()
DLegalizeDAG.cpp1244 case ISD::SINT_TO_FP: in LegalizeOp()
2619 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2628 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2674 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2745 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2746 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
3145 case ISD::SINT_TO_FP: in ExpandNode()
3147 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
4217 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
4273 case ISD::SINT_TO_FP: in PromoteNode()
[all …]
DSelectionDAGDumper.cpp253 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
DLegalizeVectorTypes.cpp97 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
442 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
652 case ISD::SINT_TO_FP: in SplitVectorResult()
1434 case ISD::SINT_TO_FP: in SplitVectorOperand()
2078 case ISD::SINT_TO_FP: in WidenVectorResult()
2981 case ISD::SINT_TO_FP: in WidenVectorOperand()
DFastISel.cpp244 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1626 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
DLegalizeIntegerTypes.cpp896 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; in PromoteIntegerOperand()
2667 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; in ExpandIntegerOperand()
3050 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
3052 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h402 SINT_TO_FP, enumerator
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); in LowerSDIV24()
530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib); in LowerSDIV24()
DR600ISelLowering.cpp414 ConversionOp = ISD::SINT_TO_FP; in LowerSELECT_CC()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
364 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
371 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
382 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
388 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
511 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
638 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1842 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1843 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1844 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1847 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
1848 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
309 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1554 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2174 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1524 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1526 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
2936 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3346 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3353 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()

12