| /external/libhevc/common/arm64/ |
| D | ihevc_inter_pred_chroma_copy.s | 124 ST1 {v0.s}[0],[x1] //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
127 ST1 {v0.s}[0],[x6],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
130 ST1 {v0.s}[0],[x6],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
133 ST1 {v0.s}[0],[x6],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
155 ST1 {v0.s}[0],[x1] //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
158 ST1 {v0.s}[0],[x6],x3 //vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
178 ST1 {v0.8b},[x1],#8 //vst1_u8(pu1_dst_tmp, tmp_src)
180 ST1 {v1.8b},[x6],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
183 ST1 {v2.8b},[x6],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
185 ST1 {v3.8b},[x6],x3 //vst1_u8(pu1_dst_tmp, tmp_src)
[all …]
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| D | ihevc_mem_fns.s | 84 ST1 {v0.8b},[x0],#8
113 ST1 {v0.8b},[x0],#8
156 ST1 {v0.8b},[x0],#8
185 ST1 {v0.8b},[x0],#8
229 ST1 {v0.8h},[x0],#16
258 ST1 {v0.8h},[x0],#16
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| D | ihevc_sao_band_offset_luma.s | 120 ST1 {v0.8b},[x3],#8 //Store to pu1_src_top[col]
225 ST1 {v13.8b},[x4],x1 //vst1_u8(pu1_src_cpy, au1_cur_row)
227 ST1 {v15.8b},[x5] //vst1_u8(pu1_src_cpy, au1_cur_row)
230 ST1 {v17.8b},[x6],x1 //vst1_u8(pu1_src_cpy, au1_cur_row)
233 ST1 {v19.8b},[x10] //vst1_u8(pu1_src_cpy, au1_cur_row)
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| D | ihevc_sao_edge_offset_class1.s | 137 ST1 { v30.16b},[x3],#16 //vst1q_u8(pu1_src_top[col])
209 ST1 { v20.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
215 ST1 { v30.16b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
248 ST1 { v30.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
271 ST1 {v30.8b},[x3] //vst1_u8(pu1_src_top[col])
322 ST1 {v20.8b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
326 ST1 {v30.8b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
352 ST1 {v30.8b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
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| D | ihevc_sao_edge_offset_class1_chroma.s | 161 ST1 { v30.16b},[x3],#16 //vst1q_u8(pu1_src_top[col])
257 ST1 { v20.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
263 ST1 { v30.16b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
308 ST1 { v30.16b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
333 ST1 {v30.8b},[x3] //vst1_u8(pu1_src_top[col])
409 ST1 {v20.8b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
413 ST1 {v30.8b},[x10],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
451 ST1 {v30.8b},[x10],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
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| D | ihevc_sao_edge_offset_class0_chroma.s | 128 ST1 {v0.8b},[x3],#8 //Store to pu1_src_top[col]
298 ST1 {v21.8b},[x12],#8 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
299 ST1 {v23.8b},[x12],x1
309 ST1 {v28.8b, v29.8b},[x12],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
458 ST1 {v18.8b},[x12],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
469 ST1 {v28.8b},[x12],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
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| D | ihevc_sao_edge_offset_class0.s | 112 ST1 {v0.8b},[x3],#8 //Store to pu1_src_top[col]
247 ST1 {v18.8b, v19.8b},[x12],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
252 ST1 {v0.8b, v1.8b},[x12],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
332 ST1 {v28.8b},[x12],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
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| D | ihevc_sao_band_offset_chroma.s | 137 ST1 {v0.8b},[x3],#8 //Store to pu1_src_top[col]
393 ST1 {v5.8b},[x4] //vst1q_u8(pu1_src_cpy, au1_cur_row)
401 ST1 {v13.8b},[x5] //vst1q_u8(pu1_src_cpy, au1_cur_row)
410 ST1 {v17.8b},[x6],x1 //vst1q_u8(pu1_src_cpy, au1_cur_row)
416 ST1 {v21.8b},[x7] //vst1q_u8(pu1_src_cpy, au1_cur_row)
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| D | ihevc_sao_edge_offset_class2.s | 110 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
351 ST1 { v20.16b},[x0],x1 //I vst1q_u8(pu1_src_cpy, pu1_cur_row)
460 ST1 { v26.16b},[x0],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
466 ST1 { v20.16b},[x0],x1 //III vst1q_u8(pu1_src_cpy, pu1_cur_row)
526 ST1 { v20.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
661 ST1 { v28.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
787 ST1 {v30.8b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
833 ST1 {v0.8b},[x3],#8 //pu1_src_top[col] = au1_src_top_tmp[col]
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| D | ihevc_sao_edge_offset_class3.s | 110 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
380 ST1 { v20.16b},[x0],x1 //I vst1q_u8(pu1_src_cpy, pu1_cur_row)
481 ST1 { v28.16b},[x0],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
517 ST1 { v20.16b},[x0],x1 //III vst1q_u8(pu1_src_cpy, pu1_cur_row)
557 ST1 { v20.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
699 ST1 { v28.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
832 ST1 {v30.8b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
873 ST1 {v0.8b},[x3],#8 //pu1_src_top[col] = au1_src_top_tmp[col]
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| D | ihevc_sao_edge_offset_class3_chroma.s | 121 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
496 ST1 { v20.16b},[x0],x1 //I vst1q_u8(pu1_src_cpy, pu1_cur_row)
637 ST1 { v28.16b},[x0],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
667 ST1 { v20.16b},[x0],x1 //III vst1q_u8(pu1_src_cpy, pu1_cur_row)
744 ST1 { v20.16b},[x0],x1 //III vst1q_u8(pu1_src_cpy, pu1_cur_row)
921 ST1 { v28.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
1097 ST1 {v30.8b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
1140 ST1 {v0.8b},[x3],#8 //pu1_src_top[col] = au1_src_top_tmp[col]
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| D | ihevc_sao_edge_offset_class2_chroma.s | 124 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
515 ST1 { v20.16b},[x0],x1 //I vst1q_u8(pu1_src_cpy, pu1_cur_row)
651 ST1 { v28.16b},[x0],x1 //II vst1q_u8(pu1_src_cpy, pu1_cur_row)
680 ST1 { v20.16b},[x0],x1 //III vst1q_u8(pu1_src_cpy, pu1_cur_row)
753 ST1 { v20.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
907 ST1 { v28.16b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
1060 ST1 {v28.8b},[x0],x1 //vst1q_u8(pu1_src_cpy, pu1_cur_row)
1105 ST1 {v0.8b},[x3],#8 //pu1_src_top[col] = au1_src_top_tmp[col]
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| /external/libhevc/decoder/arm64/ |
| D | ihevcd_fmt_conv_420sp_to_420sp.s | 118 ST1 {v0.8b},[x2],#8
119 ST1 {v1.8b},[x2],#8
120 ST1 {v2.8b},[x2],#8
121 ST1 {v3.8b},[x2],#8
138 ST1 {v0.8b},[x2],#8
139 ST1 {v1.8b},[x2],#8
140 ST1 {v2.8b},[x2],#8
141 ST1 {v3.8b},[x2],#8
174 ST1 {v0.8b},[x2],#8
175 ST1 {v1.8b},[x2],#8
[all …]
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| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 275 ST1 {v14.4s},[x2],#16
276 ST1 {v20.4s},[x2],#16
277 ST1 {v16.4s},[x2],#16
278 ST1 {v22.4s},[x2],#16
341 ST1 {v14.4s},[x8],#16
342 ST1 {v20.4s},[x8],#16
343 ST1 {v16.4s},[x8],#16
344 ST1 {v22.4s},[x8],#16
438 ST1 {v14.4s},[x2],#16
439 ST1 {v20.4s},[x2],#16
[all …]
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| D | ihevcd_fmt_conv_420sp_to_420p.s | 174 ST1 {v0.8b},[x3],#8
175 ST1 {v1.8b},[x5],#8
190 ST1 {v0.8b},[x3],#8
191 ST1 {v1.8b},[x5],#8
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| /external/llvm/test/CodeGen/Mips/ |
| D | helloworld.ll | 4 …-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1
43 ; ST1: li ${{[0-9]+}}, %hi($.str)
44 ; ST1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
45 ; ST1: addiu ${{[0-9]+}}, %lo($.str)
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| /external/llvm/test/CodeGen/X86/ |
| D | merge-store-partially-alias-loads.ll | 27 ; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ST2]], [[LD1]], t{{[0-9]+}}, undef:i64
28 ; DBGDAG: X86ISD::RET_FLAG [[ST1]],
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| /external/llvm/docs/ |
| D | BigEndianNEON.rst | 109 …age over ``LD1`` and ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the individual lane…
152 …` was chosen as the canonical vector load instruction (and by inference, ``ST1`` for vector stores…
179 …ence such as that in the figure on the right. The mismatched ``LD1`` and ``ST1`` cause the stored …
200 ST1 v0.2d, [y]
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| /external/opencv3/modules/imgproc/src/opencl/ |
| D | boxFilter.cl | 56 #define loadpix(addr) vload3(0, (__global const ST1 *)(addr))
58 #define SRCSIZE (int)sizeof(ST1)*cn
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 2804 // Various unary fpstack operations default to operating on on ST1.
2806 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2807 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
2808 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2809 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2810 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
2811 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2812 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2813 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2814 def : InstAlias<"fxch", (XCH_F ST1), 0>;
[all …]
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| D | X86InstrControl.td | 21 // ST1 arguments when returning values on the x87 stack.
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| D | X86RegisterInfo.td | 243 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1992 // We must use ST1 to store vectors in big-endian.
2005 // We must use ST1 to store vectors in big-endian.
2077 // We must use ST1 to store vectors in big-endian.
2103 // We must use ST1 to store vectors in big-endian.
2174 // We must use ST1 to store vectors in big-endian.
2198 // We must use ST1 to store vectors in big-endian.
4943 defm ST1 : SIMDSt1Multiple<"st1">;
5066 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
5067 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5068 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
[all …]
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| /external/vixl/doc/ |
| D | supported-instructions.md | 3769 ### ST1 ### subsection
3778 ### ST1 ### subsection
3789 ### ST1 ### subsection
3797 ### ST1 ### subsection
3807 ### ST1 ### subsection
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| /external/llvm/docs/TableGen/ |
| D | index.rst | 68 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
|