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Searched refs:SUBREG_TO_REG (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td221 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
223 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
225 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
229 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
231 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
233 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
254 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
256 (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
258 (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
262 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
[all …]
DAArch64InstrInfo.td536 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
1395 (SUBREG_TO_REG (i64 0),
1400 (SUBREG_TO_REG (i64 0),
1555 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1557 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1563 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1573 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1575 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1577 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1579 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
[all …]
DAArch64FastISel.cpp1834 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
3818 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3971 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4092 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4201 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
4260 TII.get(AArch64::SUBREG_TO_REG), Src64) in emitIntExt()
4357 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4400 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
/external/llvm/lib/Target/X86/
DX86InstrExtension.td162 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
165 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
167 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
170 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
172 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
175 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
180 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
182 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
293 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
307 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1158 (SUBREG_TO_REG (i64 0),
1176 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1178 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1180 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1182 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1195 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1197 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
[all …]
DX86InstrAVX512.td1405 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1406 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1412 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1413 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1622 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1623 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1627 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1628 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1885 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1886 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
[all …]
DX86InstrSSE.td510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
632 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
[all …]
DX86ISelDAGToDAG.cpp1588 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in selectLEA64_32Addr()
1602 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in selectLEA64_32Addr()
2693 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
2747 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
DX86FastISel.cpp1368 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG), in X86SelectZExt()
1717 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) in X86SelectDivRem()
3318 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
3346 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) in X86MaterializeInt()
/external/llvm/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td148 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
151 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
157 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
160 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
DMipsSEISelDAGToDAG.cpp260 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT, in selectAddESubE()
DMipsSEISelLowering.cpp3137 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FW()
3171 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FD()
3255 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_DF_VIDX()
DMips32r6InstrInfo.td486 // We must insert a SUBREG_TO_REG around $fd_in
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp118 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) in processBlock()
DPPCInstrVSX.td836 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
846 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
847 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
1573 (v16i8 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64))>;
1575 (v8i16 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64))>;
1577 (v4i32 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64))>;
1579 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;
DPPCVSXSwapRemoval.cpp388 case PPC::SUBREG_TO_REG: { in gatherVectorInstructions()
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
DPeepholeOptimizer.cpp486 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp265 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
305 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
DInstrEmitter.cpp528 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
561 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
728 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1908 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2129 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2158 POpc == TargetOpcode::SUBREG_TO_REG) { in unscheduledNode()
2600 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2973 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h777 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
818 case TargetOpcode::SUBREG_TO_REG:
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td304 // we can use a SUBREG_TO_REG.
306 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
1131 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;

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