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Searched refs:SchedWrites (Results 1 – 8 of 8) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.h235 std::vector<CodeGenSchedRW> SchedWrites; variable
309 assert(Idx < SchedWrites.size() && "bad SchedWrite index"); in getSchedWrite()
310 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite"); in getSchedWrite()
311 return SchedWrites[Idx]; in getSchedWrite()
DCodeGenSchedule.cpp200 SchedWrites.resize(1); in collectSchedRW()
275 SchedWrites.emplace_back(SchedWrites.size(), *SWI); in collectSchedRW()
283 for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(), in collectSchedRW()
284 WE = SchedWrites.end(); WI != WE; ++WI) { in collectSchedRW()
301 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) { in collectSchedRW()
303 SchedWrites[WIdx].dump(); in collectSchedRW()
336 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
456 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findRWForSequence()
478 unsigned RWIdx = IsRead ? SchedReads.size() : SchedWrites.size(); in findOrInsertRW()
483 SchedWrites.push_back(SchedRW); in findOrInsertRW()
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/external/llvm/include/llvm/Target/
DTargetSchedule.td215 // SchedWrites with additive latency. This allows a single operand to
217 // SchedWrites.
253 // be used instead to define subtarget specific SchedWrites and map
255 // itinerary classes to the subtarget's SchedWrites.
308 // A ReadAdvance may be associated with a list of SchedWrites
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td54 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedSandyBridge.td67 // Many SchedWrites are defined in pairs with and without a folded load.
DX86ScheduleBtVer2.td72 // Many SchedWrites are defined in pairs with and without a folded load.
DX86Schedule.td32 // Multiclass that produces a linked pair of SchedWrites.
DX86SchedHaswell.td77 // Many SchedWrites are defined in pairs with and without a folded load.