Searched refs:SecondReg (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2010 unsigned &SecondReg, in CanFormLdStDWord() argument
2072 SecondReg = Op1->getOperand(0).getReg(); in CanFormLdStDWord()
2073 if (FirstReg == SecondReg) in CanFormLdStDWord()
2169 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2177 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2185 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2191 .addReg(SecondReg, RegState::Define) in RescheduleOps()
2205 .addReg(SecondReg) in RescheduleOps()
2222 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2223 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4589 int SecondReg = tryParseRegister(); in tryParseGPRSeqPair() local
4590 if (SecondReg ==-1) { in tryParseGPRSeqPair()
4594 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || in tryParseGPRSeqPair()
4595 (isXReg && !XRegClass.contains(SecondReg)) || in tryParseGPRSeqPair()
4596 (isWReg && !WRegClass.contains(SecondReg))) { in tryParseGPRSeqPair()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 766 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect() local
783 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
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