| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 197 unsigned ShiftAmount; member
349 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
702 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
740 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImmNeg()
1285 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0; in addAddSubImmNegOperands()
1681 unsigned ShiftAmount, in CreateShiftedImm() argument
1686 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2297 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2303 ShiftAmount = 12; in tryParseAddSubImm()
2307 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
[all …]
|
| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2331 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; in SimplifyICmpInst() local
2332 Lower = CI2->getValue().shl(ShiftAmount); in SimplifyICmpInst()
2336 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; in SimplifyICmpInst() local
2338 Upper = CI2->getValue().shl(ShiftAmount) + 1; in SimplifyICmpInst()
2347 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2349 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2350 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
2361 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2363 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2367 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 758 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
765 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
769 ShiftAmount -= 1; in LowerShifts()
772 while (ShiftAmount--) in LowerShifts()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 845 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
847 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
848 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
|
| D | LegalizeDAG.cpp | 412 SDValue ShiftAmount = in ExpandUnalignedStore() local
416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
580 SDValue ShiftAmount = in ExpandUnalignedLoad() local
583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCasts.cpp | 457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
459 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
470 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1500 void emitAppropriateDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, in emitAppropriateDSLL() argument
1502 if (ShiftAmount >= 32) { in emitAppropriateDSLL()
1503 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, in emitAppropriateDSLL()
1508 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Instructions); in emitAppropriateDSLL()
2268 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
2269 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; in loadImmediate()
2271 emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, Instructions); in loadImmediate()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1916 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
1951 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
1952 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
1959 if (ShlImm - ShiftAmount != 0 && !BiggerPattern) in isBitfieldPositioningOp()
1961 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
|
| D | AArch64ISelLowering.cpp | 7692 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
7704 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
8296 int64_t ShiftAmount; in tryCombineShiftImm() local
8306 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
8308 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
8339 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) { in tryCombineShiftImm()
8342 DAG.getConstant(-ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
8343 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) { in tryCombineShiftImm()
8346 DAG.getConstant(ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 205 unsigned &ShiftAmount);
4137 const MCExpr *ShiftAmount; in parsePKHImm() local
4140 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
4144 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
4220 const MCExpr *ShiftAmount; in parseShifterImm() local
4222 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
4226 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
4282 const MCExpr *ShiftAmount; in parseRotImm() local
4284 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
4288 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1319 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32); in LowerLOAD() local
1320 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); in LowerLOAD()
1341 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount); in LowerLOAD()
|