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Searched refs:ShiftOpc (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h27 enum ShiftOpc { enum
45 static inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
118 static inline ShiftOpc getSORegShOp(unsigned Op) { in getSORegShOp()
119 return (ShiftOpc)(Op & 7); in getSORegShOp()
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
419 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
420 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
DARMMCCodeEmitter.cpp205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1084 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1137 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1312 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1357 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1479 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
DARMISelDAGToDAG.cpp96 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
472 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
563 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
587 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
699 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
851 ARM_AM::ShiftOpc ShOpcVal = in SelectAddrMode2Worker()
917 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1398 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
2360 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in SelectV6T2BitfieldExtractOp()
DARMFastISel.cpp163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2682 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2709 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2753 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
DARMBaseInstrInfo.cpp184 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
DARMISelLowering.cpp11025 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp776 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
814 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
831 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
860 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
495 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
505 ARM_AM::ShiftOpc ShiftTy;
515 ARM_AM::ShiftOpc ShiftTy;
522 ARM_AM::ShiftOpc ShiftTy;
2542 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
2556 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
2688 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
2706 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
2979 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
399 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1138 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1177 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
1531 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
1576 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5808 unsigned ShiftOpc = Shift.getOpcode(); in tryLowerToSLI() local
5809 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) in tryLowerToSLI()
5811 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR; in tryLowerToSLI()