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Searched refs:Shuff (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dfold-vector-sext-crash2.ll8 %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
9 ret <2 x i256> %Shuff
30 %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
31 ret <2 x i256> %Shuff
52 %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
53 ret <2 x i256> %Shuff
74 %Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
75 ret <2 x i256> %Shuff
Dselectiondag-crash.ll8 …%Shuff = shufflevector <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>,…
9 …%Shuff14 = shufflevector <8 x i32> %Shuff, <8 x i32> %Shuff, <8 x i32> <i32 7, i32 9, i32 11, i32 …
10 …%Shuff35 = shufflevector <8 x i32> %Shuff14, <8 x i32> %Shuff, <8 x i32> <i32 undef, i32 1, i32 3,…
Dvbinop-simplify-bug.ll19 …%Shuff = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32…
20 %B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
Dliveness-local-regalloc.ll77 …%Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 5, i32…
Dcrash.ll325 …%Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32…
329 %B16 = frem <8 x double> zeroinitializer, %Shuff
330 %E19 = extractelement <8 x double> %Shuff, i32 5
Dfold-vector-shuffle-crash.ll28 …%Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 7, i32…
217 %I144 = insertelement <4 x i64> %Shuff, i64 %4, i32 3
/external/llvm/test/CodeGen/AArch64/
Darm64-vshuffle.ll8 %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
14 ret <8 x i1> %Shuff
31 %Shuff = shufflevector <8 x i1> zeroinitializer,
35 ret <8 x i1> %Shuff
42 …%Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1…
46 ret <16 x i1> %Shuff
70 %Shuff = shufflevector <16 x i1> zeroinitializer,
75 ret <16 x i1> %Shuff
Darm64-2013-02-12-shufv8i8.ll3 ;CHECK-LABEL: Shuff:
6 define <8 x i8 > @Shuff(<8 x i8> %in, <8 x i8>* %out) nounwind ssp {
/external/llvm/test/CodeGen/PowerPC/
Dset0-v8i16.ll6 …%Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26,…
7 …%Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 und…
16 %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff
Dstd-unal-fi.ll8 …%Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,…
14 … -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 2…
/external/llvm/test/CodeGen/Mips/msa/
Dllvm-stress-s1704963983.ll20 …%Shuff = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 5, i32…
30 …%Shuff7 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff, <8 x i32> <i32 13, i32 15, i3…
35 %Cmp10 = icmp uge <8 x i64> %Shuff, zeroinitializer
39 …%Shuff13 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff, <8 x i32> <i32 9, i32 11, i3…
42 %Tr = trunc <8 x i64> %Shuff to <8 x i32>
63 …%Shuff28 = shufflevector <8 x i64> zeroinitializer, <8 x i64> %Shuff, <8 x i32> <i32 13, i32 15, i…
95 %Sl53 = select i1 %Cmp, <8 x i64> %Shuff, <8 x i64> %Shuff
Dllvm-stress-s2704903805.ll19 %Shuff = shufflevector <1 x i8> <i8 -1>, <1 x i8> <i8 -1>, <1 x i32> undef
58 %Shuff22 = shufflevector <1 x i8> <i8 -1>, <1 x i8> %Shuff, <1 x i32> zeroinitializer
74 %Shuff35 = shufflevector <1 x i8> %Shuff, <1 x i8> <i8 -1>, <1 x i32> zeroinitializer
89 %Sl45 = select i1 true, <1 x i8> %Shuff, <1 x i8> %I43
90 %Cmp46 = icmp sge <1 x i8> %I36, %Shuff
121 %Sl67 = select i1 %Tr, <1 x i8> %Shuff, <1 x i8> %I23
Dllvm-stress-s1935737938.ll20 …%Shuff = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32…
49 %I21 = insertelement <2 x i32> %Shuff, i32 135673, i32 0
55 %E26 = extractelement <2 x i32> %Shuff, i32 1
98 %Shuff55 = shufflevector <2 x i32> %Shuff, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 2>
125 %I71 = insertelement <2 x i32> %Shuff, i32 %E26, i32 0
Dllvm-stress-s997348632.ll20 …%Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef,…
23 %Sl = select i1 false, <4 x i64> %Shuff, <4 x i64> %Shuff
113 %E63 = extractelement <4 x i64> %Shuff, i32 2
131 %E71 = extractelement <4 x i64> %Shuff, i32 0
Dllvm-stress-s3926023935.ll20 …%Shuff = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer, <4 x…
57 …%Shuff27 = shufflevector <4 x i32> %Shuff, <4 x i32> %I14, <4 x i32> <i32 6, i32 0, i32 undef, i32…
82 %I43 = insertelement <4 x i32> %Shuff, i32 %3, i32 0
121 %I65 = insertelement <4 x i32> %Shuff, i32 %3, i32 3
Dllvm-stress-s3997499501.ll20 …%Shuff = shufflevector <2 x i1> zeroinitializer, <2 x i1> zeroinitializer, <2 x i32> <i32 1, i32 3>
29 %I8 = insertelement <2 x i1> %Shuff, i1 false, i32 0
65 %E25 = extractelement <2 x i1> %Shuff, i32 1
131 %Cmp64 = icmp ne <2 x i1> %Cmp, %Shuff
Dllvm-stress-s3861334421.ll20 …%Shuff = shufflevector <8 x i64> zeroinitializer, <8 x i64> zeroinitializer, <8 x i32> <i32 3, i32…
73 %E35 = extractelement <8 x i64> %Shuff, i32 7
107 …%Shuff58 = shufflevector <8 x i64> %Shuff, <8 x i64> zeroinitializer, <8 x i32> <i32 4, i32 6, i32…
127 %Cmp71 = icmp slt <8 x i64> %I, %Shuff
Dllvm-stress-s525530439.ll20 …%Shuff = shufflevector <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 2, i…
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp15413 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT); in LowerExtendedLoad() local
15415 return Shuff; in LowerExtendedLoad()
15423 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, in LowerExtendedLoad() local
15427 Shuff = DAG.getBitcast(RegVT, Shuff); in LowerExtendedLoad()
15429 return Shuff; in LowerExtendedLoad()
26213 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, in PerformSTORECombine() local
26235 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff); in PerformSTORECombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp9872 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec, in PerformSTORECombine() local
9892 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); in PerformSTORECombine()