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Searched refs:SmallVT (Results 1 – 5 of 5) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-shrink-v1i64.ll4 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp362 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
363 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
364 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
366 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
367 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
369 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
DLegalizeIntegerTypes.cpp761 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
784 DAG.getIntPtrConstant(SmallVT.getSizeInBits(), in PromoteIntRes_XMULO()
792 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
DDAGCombiner.cpp4797 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
4798 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
4802 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
4805 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
4808 getShiftAmountTy(SmallVT))); in visitSRL()
13024 EVT SmallVT = V->getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
13025 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) in visitEXTRACT_SUBVECTOR()
13040 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() == in visitEXTRACT_SUBVECTOR()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp2520 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
2529 DAG.getValueType(SmallVT)); in PerformDAGCombine()
2532 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()