Searched refs:Src0VT (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 1132 field ValueType Src0VT = ArgVT[1];
1136 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1138 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1144 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1145 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1625 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1627 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])
1637 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1639 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1658 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1477 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
1487 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
1500 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
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