Searched refs:Src1RC (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
360 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
362 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
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| D | SIInstrInfo.td | 1055 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1057 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1062 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1080 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1084 (ins Src0RC:$src0, Src1RC:$src1)
1090 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1095 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
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| D | SIInstrInfo.cpp | 2721 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
2725 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
2729 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
2743 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
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