Searched refs:SrcLane (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 4341 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; in setExecutionDomain() local
4343 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); in setExecutionDomain()
4346 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) in setExecutionDomain()
4358 .addImm(SrcLane); in setExecutionDomain()
4389 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4393 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4400 if (SrcLane == DstLane) in setExecutionDomain()
4408 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4412 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4419 if (SrcLane != DstLane) in setExecutionDomain()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5595 int SrcLane = ShuffleMask[Anomaly]; in LowerVECTOR_SHUFFLE() local
5596 if (SrcLane >= NumInputElements) { in LowerVECTOR_SHUFFLE()
5598 SrcLane -= VT.getVectorNumElements(); in LowerVECTOR_SHUFFLE()
5600 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64); in LowerVECTOR_SHUFFLE()
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