Searched refs:TGSI_OPCODE_UMAX (Results 1 – 7 of 7) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 172 { 1, 2, 0, 0, 0, 0, COMP, "UMAX", TGSI_OPCODE_UMAX },
284 case TGSI_OPCODE_UMAX: in tgsi_opcode_infer_src_type()
332 case TGSI_OPCODE_UMAX: in tgsi_opcode_infer_dst_type()
|
| D | tgsi_exec.c | 4105 case TGSI_OPCODE_UMAX: in exec_instruction()
|
| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 382 #define TGSI_OPCODE_UMAX 132 macro
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_setup_tgsi_llvm.c | 1098 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem; in radeon_llvm_context_init()
1099 bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax"; in radeon_llvm_context_init()
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 374 case TGSI_OPCODE_UMAX: in inferSrcType()
1762 case TGSI_OPCODE_UMAX: in handleInstruction()
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_action.c | 1616 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = umax_emit_cpu; in lp_set_default_actions_cpu()
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 5381 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5555 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5729 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
|