Home
last modified time | relevance | path

Searched refs:TMP1 (Results 1 – 22 of 22) sorted by relevance

/external/pcre/dist/
Dpcre_jit_compile.c474 #define TMP1 SLJIT_R0 macro
1453 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1456 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1469 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
1472 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1482 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1485 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1491 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
1494 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1500 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->capture_last_ptr); in init_frame()
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64le-localentry.ll20 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
21 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
22 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
24 ; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
37 ; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
38 ; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
39 ; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
41 ; CHECK-NEXT: .localentry use_toc_implicit, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
Dmemcpy-vec.ll20 ; PWR7-DAG: lxvd2x [[TMP1:[0-9]+]], 0, 4
21 ; PWR7-DAG: stxvd2x [[TMP1]], 0, 3
/external/llvm/test/CodeGen/Mips/
Dselect.ll642 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
643 ; 32: c.eq.d $[[TMP]], $[[TMP1]]
652 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
653 ; 32R2: c.eq.d $[[TMP]], $[[TMP1]]
662 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
663 ; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
675 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
676 ; 64: c.eq.d $[[TMP]], $[[TMP1]]
685 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
686 ; 64R2: c.eq.d $[[TMP]], $[[TMP1]]
[all …]
/external/llvm/test/Transforms/Reassociate/
Dreassoc-intermediate-fnegs.ll3 ; CHECK: [[TMP1:%tmp.*]] = fmul fast half %a, 0xH4500
5 ; CHECK: fsub fast half [[TMP2]], [[TMP1]]
18 ; CHECK: [[TMP1:%tmp.*]] = fmul fast half %a, 0xH4500
20 ; CHECK: fadd fast half [[TMP2]], [[TMP1]]
Dmultistep.ll11 ; CHECK-NEXT: [[TMP1:%tmp.*]] = add i64 %c, %b
13 ; CHECK-NEXT: mul i64 [[TMP2]], [[TMP1]]
Dfast-multistep.ll6 ; CHECK-NEXT: [[TMP1:%tmp.*]] = fadd fast float %c, %b
8 ; CHECK-NEXT: fmul fast float [[TMP2]], [[TMP1]]
Dfast-ReassociateVector.ll19 ; CHECK-NEXT: [[TMP1:%tmp.*]] = fadd fast <2 x float> %c, %b
21 ; CHECK-NEXT: fmul fast <2 x float> [[TMP2]], [[TMP1]]
/external/libjpeg-turbo/simd/
Djsimd_arm_neon.S207 TMP1 .req r0
520 ldmia OUTPUT_BUF!, {TMP1, TMP2}
521 add TMP1, TMP1, OUTPUT_COL
523 vst1.8 {d16}, [TMP1]
526 ldmia OUTPUT_BUF!, {TMP1, TMP2}
527 add TMP1, TMP1, OUTPUT_COL
529 vst1.8 {d18}, [TMP1]
532 ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
533 add TMP1, TMP1, OUTPUT_COL
538 vst1.8 {d20}, [TMP1]
[all …]
Djsimd_arm64_neon.S235 TMP1 .req x0
589 ldp TMP1, TMP2, [OUTPUT_BUF], 16
590 add TMP1, TMP1, OUTPUT_COL
592 st1 {v16.8b}, [TMP1]
595 ldp TMP1, TMP2, [OUTPUT_BUF], 16
596 add TMP1, TMP1, OUTPUT_COL
598 st1 {v18.8b}, [TMP1]
602 ldp TMP1, TMP2, [OUTPUT_BUF], 16
604 add TMP1, TMP1, OUTPUT_COL
609 st1 {v20.8b}, [TMP1]
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dbswap1.ll22 ; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8
24 ; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]]
41 ; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8
43 ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280
/external/llvm/test/CodeGen/AArch64/
Darm64-large-frame.ll22 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
23 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
30 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
31 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
Darm64-convert-v4f64.ll26 ; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA0]].4s
27 ; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA2]].4s
28 ; CHECK: xtn v0.8b, v[[TMP1]].8h
/external/llvm/test/Transforms/InstCombine/
Dzext-bool-add-sub.ll7 ; CHECK: [[TMP1:%.*]] = sext i1 %y to i32
9 ; CHECK-NEXT: add nsw i32 [[TMP2]], [[TMP1]]
/external/llvm/test/CodeGen/X86/
Di386-shrink-wrapping.ll33 ; CHECK-NEXT: movl ([[B]]), [[TMP1:%[a-z]+]]
34 ; CHECK-NEXT: testl [[TMP1]], [[TMP1]]
/external/llvm/test/CodeGen/AMDGPU/
Dmad-combine.ll399 ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
400 ; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP1]]
406 ; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
407 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[C]], [[TMP1]]
444 ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
445 ; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
451 ; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
452 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
495 ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]]
496 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
[all …]
Dbswap.ll15 ; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
17 ; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
Dllvm.AMDGPU.bfe.i32.ll428 ; SI: v_add_i32_e32 [[TMP1:v[0-9]+]], vcc, [[TMP0]], [[BFE]]
429 ; SI: v_ashrrev_i32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
/external/llvm/test/MC/ARM/
Dltorg.s36 @ CHECK: ldr r0, .Ltmp[[TMP1:[0-9+]]]
43 @ CHECK: .Ltmp[[TMP1]]
Dldr-pseudo.s26 @ CHECK: ldr r0, .Ltmp[[TMP1:[0-9]+]]
165 @ CHECK: .Ltmp[[TMP1]]
/external/boringssl/src/crypto/ec/asm/
Dp256-x86_64-asm.pl1288 my ($M1,$T1a,$T1b,$T1c,$TMP1)=map("%ymm$_",(10..14));
1339 vpcmpeqd $INDEX, $M1, $TMP1
1348 vpand $TMP1, $T1a, $T1a
1349 vpand $TMP1, $T1b, $T1b
1350 vpand $TMP1, $T1c, $T1c
1390 my ($M1,$T1a,$T1b,$TMP1)=map("%ymm$_",(8..11));
1446 vpcmpeqd $INDEX, $M1, $TMP1
1456 vpand $TMP1, $T1a, $T1a
1457 vpand $TMP1, $T1b, $T1b
/external/llvm/test/Transforms/NaryReassociate/
Dnary-add.ll172 ; CHECK: call void @foo(i32 [[TMP1:%[a-zA-Z0-9]]])
176 ; CHECK: [[TMP2:%[a-zA-Z0-9]]] = add i32 [[TMP1]], %d