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Searched refs:V60 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h42 V4, V5, V55, V60 enumerator
94 bool hasV60TOps() const { return getHexagonArchVersion() >= V60; } in hasV60TOps()
95 bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; } in hasV60TOpsOnly()
DHexagonRegisterInfo.cpp70 case HexagonSubtarget::V60: in getCallerSavedRegs()
90 case HexagonSubtarget::V60: in getCalleeSavedRegs()
DHexagonSchedule.td20 // V60 Machine Info -
DHexagonScheduleV60.td61 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
78 // in the CVI co-processor in the Hexagon V60 machine.
309 // Hexagon V60 Resource Definitions -
DHexagonSubtarget.cpp70 { "hexagonv60", V60 }, in initializeSubtargetDependencies()
DHexagon.td28 def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
DHexagonInstrFormats.td441 // V60 Instruction Format Definitions +
447 // V60 Instruction Format Definitions +
DHexagonInstrFormatsV60.td10 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonIntrinsicsV60.td10 // This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
DHexagonInstrInfoV60.td10 // This file describes the Hexagon V60 instructions in TableGen format.
DHexagonInstrInfo.td5794 // V60 Instructions +
5800 // V60 Instructions -
/external/llvm/include/llvm/IR/
DIntrinsicsHexagon.td4986 // V60