Home
last modified time | relevance | path

Searched refs:VAL (Results 1 – 25 of 91) sorted by relevance

1234

/external/llvm/test/CodeGen/AMDGPU/
Dimm.ll130 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
131 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
140 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
141 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
150 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
151 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
160 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
161 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
170 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
171 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
[all …]
Dllvm.r600.read.local.size.ll7 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
8 ; EG: MOV * [[VAL]], KC0[1].Z
10 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
11 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
15 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
25 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
26 ; EG: MOV * [[VAL]], KC0[1].W
28 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
29 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
30 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
[all …]
Dwork-item-intrinsics.ll9 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
10 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
28 ; GCN-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
29 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
40 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
41 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y
43 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
44 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
45 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
55 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
[all …]
Dimage-resource-id.ll6 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
7 ; EG: MOV [[VAL]], literal.x
20 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
21 ; EG: MOV [[VAL]], literal.x
36 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
37 ; EG: MOV [[VAL]], literal.x
50 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
51 ; EG: MOV [[VAL]], literal.x
66 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
67 ; EG: MOV [[VAL]], literal.x
[all …]
Dimage-attributes.ll8 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
9 ; EG: MOV * [[VAL]], KC0[2].Z
21 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
22 ; EG: MOV * [[VAL]], KC0[2].Z
38 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
39 ; EG: MOV * [[VAL]], KC0[2].W
51 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
52 ; EG: MOV * [[VAL]], KC0[2].W
68 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
69 ; EG: MOV * [[VAL]], KC0[3].X
[all …]
Dllvm.AMDGPU.read.workdim.ll6 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
7 ; EG: MOV * [[VAL]], KC0[2].Z
9 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
10 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
11 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
21 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
22 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
24 ; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
Dextload.ll6 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
7 ; EG: VTX_READ_32 [[VAL]]
19 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
20 ; EG: VTX_READ_32 [[VAL]]
32 ; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
33 ; EG: LDS_WRITE * [[VAL]]
44 ; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
45 ; EG: LDS_WRITE * [[VAL]]
Dctpop.ll27 ; GCN: buffer_load_dword [[VAL:v[0-9]+]],
28 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
176 ; GCN: buffer_load_dword [[VAL:v[0-9]+]],
177 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
191 ; GCN: buffer_load_dword [[VAL:v[0-9]+]],
192 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
206 ; GCN: buffer_load_dword [[VAL:v[0-9]+]],
208 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
209 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]]
221 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]],
[all …]
Dsampler-resource-id.ll4 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
5 ; EG: MOV [[VAL]], literal.x
16 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
17 ; EG: MOV [[VAL]], literal.x
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
29 ; EG: MOV [[VAL]], literal.x
Dllvm.AMDGPU.flbit.i32.ll7 ; SI: s_load_dword [[VAL:s[0-9]+]],
8 ; SI: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]]
19 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
20 ; SI: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]]
Dfp16_to_fp.ll8 ; SI: buffer_load_ushort [[VAL:v[0-9]+]]
9 ; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
20 ; SI: buffer_load_ushort [[VAL:v[0-9]+]]
21 ; SI: v_cvt_f32_f16_e32 [[RESULT32:v[0-9]+]], [[VAL]]
/external/deqp/data/gles2/shaders/
Dpreprocessor.test155 #define VAL 2.0
156 #undef VAL sdflkjfds
157 #define VAL 1.0
161 ${POSITION_FRAG_COLOR} = vec4(VAL);
2933 #define VAL 4
2935 #if (VAL << 2) == 16
2950 #define VAL 5
2952 #if (VAL >> 1) == 2
2967 #define VAL 5
2969 #if (VAL < 6) && (-VAL < -4)
[all …]
/external/deqp/data/gles3/shaders/
Dpreprocessor.test183 #define VAL 2.0
184 #undef VAL sdflkjfds
185 #define VAL 1.0
190 ${POSITION_FRAG_COLOR} = vec4(VAL);
3654 #define VAL 4
3656 #if (VAL << 2) == 16
3673 #define VAL 5
3675 #if (VAL >> 1) == 2
3692 #define VAL 5
3694 #if (VAL < 6) && (-VAL < -4)
[all …]
/external/llvm/include/llvm/ADT/
DAPInt.h79 uint64_t VAL; ///< Used to store the <= 64 bits integer value. member
148 VAL &= mask; in clearUnusedBits()
157 return isSingleWord() ? VAL : pVal[whichWord(bitPosition)]; in getWord()
237 : BitWidth(numBits), VAL(0) { in BitWidth()
240 VAL = val; in BitWidth()
279 APInt(const APInt &that) : BitWidth(that.BitWidth), VAL(0) { in APInt()
281 VAL = that.VAL; in APInt()
287 APInt(APInt &&that) : BitWidth(that.BitWidth), VAL(that.VAL) { in APInt()
302 explicit APInt() : BitWidth(1), VAL(0) {} in APInt()
340 return VAL == ~integerPart(0) >> (APINT_BITS_PER_WORD - BitWidth); in isAllOnesValue()
[all …]
/external/valgrind/auxprogs/
Dgsl16test103 rm -f out-VAL
104 …for f in $ALL_TESTS ; do eval $GSL_VV -v --trace-children=yes "$GSL_VFLAGS" ./$f ; done) &> out-VAL
109 echo -n " Valgrind fails: " && (grep FAIL: out-VAL | wc -l)
110 echo -n " Valgrind passes: " && (grep PASS: out-VAL | wc -l)
114 (echo -n " Valgrind fails: " && (grep FAIL: out-VAL | wc -l)) >> summary.txt
115 (echo -n " Valgrind passes: " && (grep PASS: out-VAL | wc -l)) >> summary.txt
/external/autotest/client/site_tests/firmware_TouchMTB/
Dtest_conf.py10 from firmware_constants import DEV, GV, VAL
285 segment_weights = {VAL.BEGIN: 0.15,
286 VAL.MIDDLE: 0.7,
287 VAL.END: 0.15,
288 VAL.BOTH_ENDS: 0.15 + 0.15,
289 VAL.WHOLE: 0.15 + 0.7 + 0.15,
381 segments=VAL.MIDDLE)),
386 slots=0, segments=VAL.MIDDLE)),
389 slots=0, segments=VAL.BOTH_ENDS)),
437 segments=VAL.MIDDLE),
[all …]
Dfirmware_constants.py249 VAL = _Validator() variable
250 VAL.BEGIN = 'Begin'
251 VAL.MIDDLE = 'Middle'
252 VAL.END = 'End'
253 VAL.BOTH_ENDS = 'BothEnds'
254 VAL.WHOLE = 'Whole'
256 VAL.SEGMENT_LIST = list(VAL.__dict__.values())
/external/llvm/lib/Support/
DAPInt.cpp94 VAL = bigVal[0]; in initFromArray()
108 : BitWidth(numBits), VAL(0) { in APInt()
113 : BitWidth(numBits), VAL(0) { in APInt()
118 : BitWidth(numbits), VAL(0) { in APInt()
138 VAL = 0; in AssignSlowCase()
145 VAL = RHS.VAL; in AssignSlowCase()
157 VAL = RHS; in operator =()
170 ID.AddInteger(VAL); in Profile()
199 ++VAL; in operator ++()
228 --VAL; in operator --()
[all …]
/external/libxml2/os400/
Dmake-rpg.sh31 VAL="`db2_name \"${NAME}\" nomangle`"
34 then VAL=SCHMTYPES
37 eval "VAR_${VAR}=\"${VAL}\""
38 echo "${VAR} s/${VAR}/${VAL}/g"
/external/autotest/client/site_tests/firmware_TouchMTB/tests/
Dfirmware_summary_unittest.py13 from firmware_constants import VAL
18 segment_weights = {VAL.BEGIN: 0.15,
19 VAL.MIDDLE: 0.7,
20 VAL.END: 0.15,
21 VAL.BOTH_ENDS: 0.15 + 0.15,
22 VAL.WHOLE: 0.15 + 0.7 + 0.15}
/external/llvm/test/CodeGen/SystemZ/
Dint-move-08.ll94 ; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
96 ; CHECK: st [[VAL]], 0([[REG]])
108 ; CHECK: llc [[VAL:%r[0-5]]], 0([[REG]])
109 ; CHECK: srl [[VAL]], 1
110 ; CHECK: stc [[VAL]], 1([[REG]])
124 ; CHECK: llhrl [[VAL:%r[0-5]]], garray16
125 ; CHECK: srl [[VAL]], 1
126 ; CHECK: sthrl [[VAL]], garray16+2
/external/llvm/test/Transforms/InstCombine/
Dsincospi.ll26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
31 ; CHECK: [[VAL:%[a-z0-9]+]] = load float, float* @var32
32 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float [[VAL]])
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 …ECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
68 ; CHECK: [[VAL:%[a-z0-9]+]] = load double, double* @var64
69 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
/external/clang/test/CodeGenCXX/
Ddebug-info-byval.cpp18 class VAL { class
26 void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) { in get()
/external/llvm/test/CodeGen/ARM/
D2010-05-18-PostIndexBug.ll11 ; ARM-DAG: mov [[VAL:r[0-9]+]], #0
12 ; ARM: str [[VAL]], [r[[ADDR]]], r0
16 ; THUMB-DAG: movs [[VAL:r[0-9]+]], #0
18 ; THUMB: str [[VAL]], [r[[ADDR]]]
/external/curl/tests/
Dvalgrind.pm41 open(VAL, "<$file");
42 while(<VAL>) {
113 close(VAL);

1234