| /external/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 261 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
264 if (DstReg != AMDGPU::VCC) in runOnMachineFunction()
277 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
280 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
297 assert(MI.getOperand(0).getReg() == AMDGPU::VCC && in runOnMachineFunction()
318 assert(Src2->getReg() == AMDGPU::VCC && in runOnMachineFunction()
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| D | SIRegisterInfo.td | 26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
203 (add SGPR_64, VCC, EXEC, FLAT_SCR)
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| D | SILowerControlFlow.cpp | 371 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC) in LoadM0()
372 .addReg(AMDGPU::VCC); in LoadM0()
385 .addReg(AMDGPU::VCC); in LoadM0()
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| D | SIInstrInfo.td | 597 int VCC = 0x6A;
1204 // encoding normally allows them since the implicit VCC use means
1207 // technically be possible to use VCC again as src0.
1215 // implicit VCC use.
1554 // instead of an implicit VCC as in the VOP2b format.
1686 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
1767 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1774 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1784 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1921 // only VOP instruction that implicitly reads VCC.
[all …]
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| D | CIInstructions.td | 85 // XXX - Does this set VCC?
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| D | SIInstructions.td | 383 VCC = COPY SCC
384 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
460 let Uses = [VCC] in {
469 } // End Uses = [VCC]
1786 let isCommutable = 1, Uses = [VCC, EXEC] in {
1810 } // End isCommutable = 1, Uses = [VCC, EXEC]
1932 let Uses = [EXEC], Defs = [EXEC,VCC] in {
1939 } // End Uses = [EXEC], Defs = [EXEC,VCC]
1943 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1974 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
[all …]
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| D | SIRegisterInfo.cpp | 509 case AMDGPU::VCC: in getPhysRegSubReg()
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| D | AMDGPUAsmPrinter.cpp | 357 case AMDGPU::VCC: in getSIProgramInfo()
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| D | SIInstrInfo.cpp | 373 if (DestReg == AMDGPU::VCC) { in copyPhysReg()
375 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
1421 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC || in usesConstantBus()
1438 case AMDGPU::VCC: in findImplicitSGPRRead()
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| D | SIInstrFormats.td | 109 let Defs = [VCC];
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | flat-scratch-reg.ll | 16 call void asm sideeffect "", "~{SGPR7},~{VCC}"()
34 call void asm sideeffect "", "~{SGPR7},~{VCC},~{FLAT_SCR}"()
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| D | add.ll | 141 ; use VCC. The test is designed so that %a will be stored in an SGPR and
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| /external/clang/test/CXX/concepts-ts/dcl.dcl/dcl.spec/dcl.spec.concept/ |
| D | p2.cpp | 5 template<typename T> concept constexpr bool VCC = true; // expected-error {{variable concept cannot…
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIISelLowering.cpp | 208 AMDGPU::VCC) in LowerSI_KIL()
239 AMDGPU::VCC) in LowerSI_V_CNDLT()
245 .addReg(AMDGPU::VCC) in LowerSI_V_CNDLT()
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| D | AMDGPUAsmPrinter.cpp | 80 if (reg == AMDGPU::VCC) { in EmitProgramInfo()
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| D | SIInstrInfo.td | 26 // Special bitcast node for sharing VCC register between VALU and SALU
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| D | SIInstructions.td | 79 VCC = COPY SCC
80 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
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| /external/clang/unittests/AST/ |
| D | CommentParser.cpp | 1227 VerbatimBlockComment *VCC; in TEST_F() local
1228 ASSERT_TRUE(HasVerbatimBlockAt(FC, Traits, 1, VCC, in TEST_F()
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 133 case AMDGPU::VCC: in printRegOperand()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 506 .Case("vcc", AMDGPU::VCC) in getRegForName()
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